OR-type CMOS logic circuit with fast precharging

Electrical transmission or interconnection systems – Plural supply circuits or sources – One source floats across or compensates for other source

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Details

365203, 365204, 365104, 307585, H03K 19017, H03K 19094, G11C 700, G11C 1140

Patent

active

048990663

ABSTRACT:
A complementary metal oxide semiconductor logic circuit comprises a signal line OR-connecting a plurality of MOS transistors which are turned on/off by a plurality of decoder outputs. The signal line is divided by a MOS-FET in two portions including a portion on an output side provided with an inverter and an OR-connected transistors side, so that respective portions of the signal line as divided are precharged by separate precharging MOS transistors.

REFERENCES:
patent: 4592021 (1986-05-01), Suzuki et al.
"Introduction to MOS LSI Design", J. Mavor et al, published by University of Edinburgh & translated into Japanese by T. Sugano & published by Sangyo Tosyo Co., Ltd., Apr. 1984, pp. 124-125.

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