OR-plane memory cell array for flash memory with bit-based write

Details OR-plane memory cell array for flash memory with bit-based write OR-plane memory cell array for flash memory with bit-based write

1996-11-14

1998-05-05

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular connection

36518513, G11L 1600

Patent

active

057485380

ABSTRACT:
A memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes a plurality of transistor cells arranged in rows and columns. The sources of transistor cells in the same memory block are connected to a main source line through a control gate, as are the drains. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected transistor cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected transistor cells. The associated circuitry for bit-based writing, as well as methods of programming and erasing the memory cell array, with over-program and over-erase repair capability, are also disclosed.

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