Optoelectric device having a very low stray capacitance and its

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction

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257 95, 257 96, 257 97, 437127, 437129, 437905, 372 45, 372 46, 372 48, H01L 3300

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active

054401470

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BRIEF SUMMARY
This application is a Rule 371 continuation of PCT/FR92/00338, filed Apr. 15, 1992.


DESCRIPTION

The present invention relates to an optoelectronic device having a very low stray capacitance and its production process. It more particularly applies to the production of semiconductor lasers, optical modulators or amplifiers having an electrically controlled and very high switching speed.
The buried ridge stripe or BRS structure is described in the article by J. C. Bouley et al, published in Proceedings of the 9th IEEE International Laser Conference, p. 54, 1984 and which makes it possible to produce optoelectronic devices having a high switching speed and in particular semiconductor lasers.
A semiconductor laser produced according to the BRS method has a stripe including an active layer with a small gap buried in a wider gap confinement layer. The confinement is then electrical and optical. The stripe guides the light beam produced during electrical excitation. The optical cavity necessary for obtaining the laser effect is constituted by the cleaved or etched ends of the strip.
The optoelectronic devices produced according to the BRS method respond very rapidly to electrical excitations. The ultimate response time limited by the relaxation process of the carriers in the conduction and valence bands. It can therefore theoretically reach durations of approximately 1 picosecond. However, such an operating speed is more severely limited by the actual structure of the component and its parasitic electrical elements. Generally, the parasitic circuit is equivalent to an RC circuit, in which R is the access resistance to the active zone and C a stray capacitance.
FIG. 1 diagrammatically shows a known laser structure described in the article by J. E. Bowers al, published in ELectronics Letters, vol.23, no.24, pp.1263-1265, 19.11.1987. This device is derived from a BRS structure and has an improved response time.
A stripe 10 including an active material layer rests on an n-doped InP substrate 12. The two lateral sides of the stripe 10 are surrounded by a semi-insulating, InP, lateral confinement layer 14. A p-doped, InP, vertical confinement layer 16 is positioned vertically of the stripe 10 in a groove corresponding to the impression of the dielectric growth stopping mask used during the selective epitaxy stage for forming the layer 14. The vertical confinement layer 16 is truncated and its lateral faces are surrounded by a polyimide dielectric layer 18. The profile of the layer 16 is obtained by epitaxy on the complete structure and then etching, in accordance with a desired pattern, of the said layer 16. The upper face is covered with a contact layer 20.
The short response time (RC approximately 4 ps) of such a structure is obtained as a result of the limited contact surface between the vertical confinement layer 16 and the semi-insulating layer 14. Thus, said contact zone when large is a current loss source due to the diffusion of acceptors of the vertical confinement layer 16 into the semi-insulating layer 14, which then loses its dielectric properties.
However, this structure still suffers from a certain number of disadvantages. Thus, its construction makes use of a selective epitaxy stage for the formation of the semi-insulating, lateral confinement layer 14. The presence of a growth stopping mask of a different nature from that of the semi-insulating layer (whereof only the groove-like impression is visible in FIG. 1) is a source of disturbances (mechanical stresses) and defects in the semi-insulating material, more particularly on the mask border and therefore in direct proximity to the active layer. These disturbances and defects are responsible for current losses, thus increasing the stray capacitance of the component and in certain cases the threshold current.
Moreover, during the epitaxy stage of the vertical confinement layer 16, the diffusions of zinc (p-dopant of the layer 16) towards the semi-insulating layer 14 and conversely iron (dopant of the layer 14) towards the vertical confinement layer are

REFERENCES:
patent: 4977568 (1990-12-01), Yamamoto et al.
Sasaki et al., "A2.5-MA Threshold Current Operation and a 5-GBit/S Zero-Bias Current Modulation of 1.5 .mu.m MQW-DFB Laser Diodes,".
Optical Fiber Communication Conference 1990, Technical Digest Series, vol. 1, 22 Jan. 1990, San Francisco, Calif., USA, p. 213.
Ishiguro et al., "Very Low Threshold Planar Buried Heterostructure InGaAsP/InP Laser Diodes Prepared by Three-Stage Metalorganic Chemical Vapor Deposition," Appl. Phys. Lett., vol. 51, No. 12, 21 Sep. 1987, pp. 874-876.
Miller et al., "Tertiarybutylarsine as a Substitute for AsH.sub.3 : Application to InGaAs/InP Photonic Integrated Circuits," Second International Conference-Indium Phosphide and Related Materials, 23 Apr. 1990, Denver, Colo., USA, pp. 161-164.
Bowers et al., "High-Speed, Polyimide-Based Semi-Insulating Planar Buried Heterostructures," Electronics Letters, vol. 23, No. 24, 19 Nov. 1987, pp. 1263-1265.
Razeghi et al., "CW Operation of 1.57-.mu.m Ga.sub.x In.sub.1-x As.sub.y P.sub.1-y InP Distributed Feedback Lasers Grown by Low-Pressure Metalorganic Chemical Vapor Deposition," Appl. Phys. Lett. 45(7), 1 Oct. 1984, pp. 784-786.
Pat. Abst. of Japan, vol. 15, No. 200 (E-1070) Jun. 22, 1991.

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