Option/sequence selection circuit with sequence selection first

Details Option/sequence selection circuit with sequence selection first Option/sequence selection circuit with sequence selection first

1989-06-28

1991-03-26

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307481, 377 76, 377 79, H03K 17296

Patent

active

050032011

ABSTRACT:
A circuit is provided having a plurality of flip flops (F.sub.l -F.sub.n) that are serially connected for executing sequential operations under the control of a clock. The outputs (Q.sub.l -Q.sub.n) of the flip flops (F.sub.l -F.sub.n) are connected to corresponding inputs (I.sub.l -I.sub.n) of a binary decoder and the sequential outputs (O.sub.1 -O.sub.2) of the binary decoder execute the sequential selection. However, when an optional operation is selected during the execution of the sequential selection, a first switch switches the state of the clock terminals of the flip flops to a "high level" so that the flip flops memorize the state of the interrupted sequence selection. Subsequently, the option selection is carried out by the manipulation of a set of switches. Upon completion of the option selection, the first switch is switched back so that the execution of the interrupted sequence selection continues.

REFERENCES:
patent: 3824480 (1974-07-01), Eshraghian
patent: 4027175 (1977-05-01), Hurst
patent: 4366393 (1982-12-01), Kasuya
patent: 4568841 (1986-02-01), Mayhew
patent: 4802120 (1989-01-01), McCoy
patent: 4873671 (1989-10-01), Kowshik et al.
patent: 4877974 (1989-10-01), Kawai et al.

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