Optimum timing of write and read clock paths

Details Optimum timing of write and read clock paths Optimum timing of write and read clock paths

2008-05-30

2010-10-19

Raymond, Edward (Department: 2857)

Data processing: measuring, calibrating, or testing

Calibration or correction system

Timing

Reexamination Certificate

active

07818135

ABSTRACT:
An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test bus between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies.

REFERENCES:
patent: 5396463 (1995-03-01), Kim et al.
patent: 5742185 (1998-04-01), Lee
patent: 6959256 (2005-10-01), Basto
patent: 7005875 (2006-02-01), Natarajan et al.
patent: 2010/0064074 (2010-03-01), Hansquine et al.

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