Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
1998-07-08
2003-03-18
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S676000, C257S690000, C257S691000, C257S692000, C257S773000, C257S786000
Reexamination Certificate
active
06534878
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention is directed to a semiconductor element composed of an integrated semiconductor chip with at least one power MOSFET or a power bipolar transistor and a signal-processing circuit that processes a weak-current signal, whereby each circuit comprises terminal surfaces that are connected to a conductor frame via a plurality of bond wires.
Such a component is disclosed, for example, by European reference EP 0 446 937 B1. The subject matter of European EP reference 0 446 937 B1 is herewith expressly incorporated by reference into the present application.
The semiconductor components shown therein (
FIGS. 1 and 2
) are usually low-impedance semiconductor switches wherein the resistance of the line connection between the semiconductor chip and the conductor frame is no longer negligible. This line also limits the maximally allowable load current.
Further, the metallization that connects the power transistor to the bond wire exhibits a clear resistance part due to the large area of the semiconductor chip. Since the current density in the metallization is very high around the bond contact, this also leads to a non-uniform temperature distribution on the chip and to a reduction of the service life of the chip.
The solutions known from the Prior Art provide one or more bond wires, all of which are contacted to the outer conductor frame, for the line connection. The plurality and thickness of the bond wires is based on the on-state d.c. resistance of the semiconductor switch and on the available bond area on the conductor frame.
Both the resistance of the bond wire as well as the resistance of the metallization are highest when only one bond wire is employed. The result is still unsatisfactory when two contact locations on the conductor frame or, respectively, two bond wires are employed.
The capture area of the bond wires differ greatly, so that the utilization of the semiconductor chip is reduced. The current conduction through the two bond wires is likewise asymmetrical, so that the load current allowed overall through the bond wires does not rise linearly.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to improve a semiconductor component of the species initially cited to such effect that a significantly better line connection can be produced between the power part of a semiconductor switch and the conductor frame.
This object is inventively achieved in that the power MOSFET or the power bipolar transistor comprises an input/output at the back side of the semiconductor chip and comprises two symmetrically arranged inputs/outputs at the front side, and in that the symmetrically arranged inputs/outputs at the front side are symmetrically connected to bond wires at both sides of the conductor frame. A noticeably improved connection is thereby produced. The optimization of this connection ensues via the bond wires at both sides of the conductor frame that are symmetrical and divide the semiconductor chip into two halves. The length of the bond wires is the same and shorter than in the asymmetrical connection known from the Prior Art since the chip is bonded from two sides.
The advantage of this line connection is comprised in the better division of current on the semiconductor chip due the optimally possible positioning of the bond contact on the metallization layer of the chip given this configuration. Since the currents through the bond wires are the same, the load current allowed overall through the bond wires increases linearly. The bond wire resistance is reduced. Overall, this connection yields a clearly reduced on-state d.c. resistance and a higher loadability given pre-conditions that are otherwise the same.
REFERENCES:
patent: 5029267 (1991-07-01), Masuda et al.
patent: 0446937 (1992-12-01), None
PROFET “Online” Updated Mar. 4, 1997, Available from Internet: <URL:HTTP://WWW.Siemens.DE/Semiconductor/Products/36/3634.HTM XP002063574, pp. 1-1 through 2-7.
Electronics, vol. 59, No. 27, Jul. 24, 1986, S. Zollo, “The Boom Starts in Smart Power Products”, XP 000051602, pp. 97-101.
Motorola, Electronic, vol. 42, No. 21, XP 002063575, Oct. 19, 1993, Smartmos-Technologie: Was Macht Motorola?, pp. 28-29.
Electronics, vol. 40, No. 14, Jul. 9, 1991, Guenther van Treek et al, Hochstrom-Motortreiber-ICS Ein Schritt Zur Multiplextechnik Im Auto, XP 000241415, pp. 58-61.
EDN—Electrical Design News, vol. 33, No. 7, Mar. 31, 1988, XP 000118770, Dave Pryce, Associate Editor, “SMART-POWER”, pp. 113-123.
Sander Rainald
Xu Chihao
Lee Eddie
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
Warren Matthew E.
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