Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-01-04
2011-01-04
Mai, Son L (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S233100
Reexamination Certificate
active
07864625
ABSTRACT:
A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.
REFERENCES:
patent: 5389843 (1995-02-01), McKinney
patent: 5596539 (1997-01-01), Passow et al.
patent: 6417715 (2002-07-01), Hamamoto et al.
patent: 6549041 (2003-04-01), Waldrop
patent: 6760269 (2004-07-01), Nakase et al.
patent: 6889336 (2005-05-01), Schoenfeld et al.
patent: 7212053 (2007-05-01), Gomm et al
patent: 7495487 (2009-02-01), Ma et al.
patent: 2005/0041486 (2005-02-01), Cooper
patent: 2005/0237848 (2005-10-01), Takahashi et al.
patent: 2008/0037338 (2008-02-01), Chen et al.
patent: 3157011 (1991-05-01), None
D. Sengupta et al., “Generalized Power-Delay Metrics in Deep Submicron CMOS Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, No. 1, Jan. 2007.
K. Osada et al., “Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell,” ISSCC, Feb. 2001 pp. 168-169, 443.
Carpenter Gary D.
Kuang Jente B.
Nowka Kevin J.
Pang Liang-Teck
Handelsman Libby Z.
International Business Machines - Corporation
Mai Son L
Musgrove Jack V.
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