Optimizing page size in mixed memory array using address multipl

Details Optimizing page size in mixed memory array using address multipl Optimizing page size in mixed memory array using address multipl

1998-12-04

2000-03-21

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Byte or page addressing

36523002, 36523003, G11C 800

Patent

active

060410167

ABSTRACT:
The present invention is a method and apparatus for addressing a memory array. The memory array has N rows of memory devices with different page sizes. A memory address corresponding to one of the N rows of memory devices is generated. A device bank address is selected corresponding to a device size and a device page size of the one of the N rows of memory devices.

REFERENCES:
patent: 5047989 (1991-09-01), Canepa et al.
patent: 5452257 (1995-09-01), Han
patent: 5488711 (1996-01-01), Hewitt et al.
patent: 5841715 (1998-11-01), Farmwald et al.

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