Optimizing method for logic circuit and logic circuit optimizing

Details Optimizing method for logic circuit and logic circuit optimizing Optimizing method for logic circuit and logic circuit optimizing

1995-10-27

1998-06-09

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

057645272

ABSTRACT:
A logic circuit partitioning system includes a logic circuit network generating portion for inputting a logical expression group and generating a logic circuit network, in which each node corresponds to each logical expression and each branch corresponds to a relationship between each logical expression, a matrix generating portion inputting the generated logical circuit network and generating a matrix, in which each row corresponds to the node in the logical circuit network and each column corresponds to an input of the logical circuit and node, and an arbitrary value is given for each element in the column corresponding to the input for the node corresponding to each row, a matrix partitioning portion for inputting the generated matrix and extracting a partial matrix which has sized in row and column greater than or equal to two and the arbitrary value at every elements therein from the matrix from the matrix generating portion, and a logic circuit network partitioning portion for partitioning partial circuit corresponding to the partial matrix extracted from the matrix, from the logic circuit network.

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Dey et al., "Corolla Based Circuit Partitiioning And Resynthesis", IEEE, Paper 37.2, pp. 607-612, (1990).
De Micheli et al., "Design Systems For VLSI Circuits Logic Synthesis and Silicon Compilation", Advanced Science Series, No. 136, pp. 197-249, (1987).

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