Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
1998-06-08
2001-04-03
Teska, Kevin J. (Department: 2763)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C716S030000
Reexamination Certificate
active
06212489
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of digital system design verification. More specifically, the present invention relates to design verification of digital systems whose development efforts are neither hardware nor software dominant.
2. Background Information
The majority of digital systems being designed today are task specific embedded systems that consist of standard and/or custom hardware as well as standard and/or custom software. Standard hardware typically includes off-the-shelf microprocessor/micro-controller, and memory etc., whereas custom hardware is implemented with programmable logic devices (PLDs), or Application Specific Integrated Circuits (ASICs). Hardware architecture binds and constrains these resource and provides a framework on which software processes execute. Standard software typically includes a real time operating system (RTOS), and configurable device drivers, whereas customer software is the embedded application. Software architecture defines how these processes communicate.
The complexity of these systems varies widely from low to high end depending on the market segment and product goals. They can be found in almost everything that we encounter in our daily lives, such as communication systems ranging from the phone on our desk, to the large switching centers, automobiles, consumer electronics, etc.
Some embedded systems are software dominant in their development effort, in that most of the design efforts are focused on implementing the functionality in software. Typically, standard or previously designed hardware are employed. Thus, even though the software dominant characteristic typically makes these systems a lot more cost sensitive, these systems can be readily validated by compiling and debugging the software under development on existing hardware, using a compiler, a debugger and other related software tools.
Other embedded systems are hardware dominant, in that most of the design efforts are focused on implementing the functionality in PLDs or ASICs. The original software content of these systems tends to be small. Typically, these embedded systems are found in applications where performance is critical. For these systems, hardware emulation and/or simulation techniques known in the art appear to adequately serve the design verification needs. In the case of emulation, the hardware is “realized” by configuring the reconfigurable logic and interconnect elements of the emulator. The configuration information are generated by “compiling” certain formal behavioral specification/description of the hardware. In the case of simulation, a simulation model would be developed. For the more “complex” hardware, since it is very difficult, if not outright impossible, to model all the behaviors of the hardware, certain accuracy are often sacrificed. For example, in the case of a microprocessor, it is often modeled by a “bus interface model”, i.e. only the different bus cycles that the processor can execute are modeled. The modeled bus cycles are driven in timed sequences, representative of typical bus transactions or bus activities for invoking specific conditions.
Embedded systems that are most difficult to validate are those that are neither software or hardware dominant, in that both parts play an equally important role in the success of the system. Due to increased time to market pressures, hardware and software are usually developed in parallel. Typically, the hardware designers would validate the hardware design using an hardware simulator or emulator. Concurrently, the software designer would validate the software using an instruction set simulator on a general purpose computer. The instruction set simulator simulates execution of compiled assembly/machine code for determining software correctness and performance at a gross level. These instruction set simulators often include facilitates for handling I/O data streams to simulate to a very limited degree the external hardware of the target design. Typically, instruction set simulators run at a speeds of ten thousand to several hundred thousand instructions per second, based on their level of detail and the performance of the host computer that they are being run on.
Traditionally, the hardware and software would not be validated together until at least a prototype of the hardware, having sufficient amount of functionality implemented and stabilized, becomes available. The software is executed with a hardware simulator, and very often in cooperation with a hardware modeler (a semiconductor tester), against which the hardware prototype is coupled. The hardware simulator provides the hardware modeler with the values on the input pins of the prototype hardware, which in turn drives these values onto the actual input pins of the prototype hardware. The hardware modeler samples the output pins of the prototype hardware and returns these values to the hardware simulator. Typically, only one to ten instructions per second can be achieved, which is substantially slower than instruction set simulation.
Recently, increasing amount of research effort in the industry has gone into improving hardware and software co-verification, such as co-simulation. New communication approaches such as “message channels” implemented e.g. using UNIX® “pipes” have been employed to facilitate communication between the hardware and software models (UNIX is a registered trademark of Santa Cruz Software, Inc.). Other efforts have allowed the models to be “interconnected” through “registers”, “queues”, etc. However, even with the improved communication techniques, and employment of less complete models, such as “bus interface models” for a microprocessor, hardware and software co-simulation known in the art remain running substantially slower than instruction set simulation.
Thus, it is desirable if hardware and software can be co-verified together at speed that is closer to instruction set simulation. As will be disclosed in more detail below, the present invention allows the user to selectively optimize the hardware and software co-verification, achieving the above discussed and other desirable results.
SUMMARY OF THE INVENTION
An optimizing hardware-software co-verification system is disclosed including a number of bus interface models, a number of memory models, and a co-verification optimization manager for co-verification hardware-software systems. In accordance to the present invention, co-verification of a hardware-software system is performed with a single coherent view of the memory of the hardware-software system. The single coherent view is transparently maintained by the co-verification optimization manager for both the hardware and software verifications performed using, the bus interface and memory models. This single coherent view includes at least one segment of the memory being viewed as configured for having selected portions of the segment to be statically or dynamically configured/reconfigured for either unoptimized or optimized accesses, wherein unoptimized accesses are performed through hardware verification, and optimized accesses are performed “directly” by the co-verification optimization manager, by-passing hardware verification, resulting in significant savings in verification time. As a result, uninteresting or inconsequential memory accesses may be optimized away by the co-verification optimization manager to significantly improve co-verification performance, with little or no impact on the accuracy of the co-verification results; and the amount of optimizations may be varied in between successive co-verification runs or during a co-verification run.
In accordance to the present invention, co-verification of a hardware-software system is also performed with or without the co-verification optimization manager optimizing verification time, which is statically or dynamically configured/reconfigured, and optionally with the co-verification optimization manager maintaining a desired clock cycle ratio between hardware and software verifications
Finch Peter
Kehoe Devon
Klein Russell
Columbia IP Law Group, LLC
Frejd Russell W.
Mentor Graphics Corporation
Teska Kevin J.
LandOfFree
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