Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth from liquid or supercritical state – Having pulling during growth
Reexamination Certificate
2001-01-11
2003-05-20
Hiteshew, Felisa (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth from liquid or supercritical state
Having pulling during growth
C117S019000, C117S028000
Reexamination Certificate
active
06565651
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of manufacturing a semiconductor wafer. More particularly, the invention provides a method of manufacturing a wafer that improves the resistance of the wafer to mechanical damage that may occur during downstream processing steps.
BACKGROUND OF THE INVENTION
Wafer breakage presents a serious problem in the manufacturing of semiconductor devices. The breakage of a single wafer may shut down a processing tool for an extended period of time while the tool is being cleaned, lowering productivity. Furthermore, in a batch process, the breakage of a single wafer may contaminate all of the other wafers in the batch, potentially ruining a large number of wafers at great expense.
One common cause of wafer breakage is the presence of microscopic damage, such as microcracks or chips, in the wafer. When a wafer with such damage is heated in a processing step, the thermal stresses formed in the wafer may cause the crack to propagate, leading to the fracture of the wafer.
Besides causing breakage, the presence of damage in the edges of a wafer can also lead to stresses in the crystalline lattice of the wafer. These stresses may result in defects, such as dislocations, that are vulnerable to slip propagation when the wafer is heated. These defects may cause the wafer to warp when it is heated, and may also impede the performance of devices fabricated on the wafer.
Many steps in both wafer manufacturing and circuit fabrication processes may damage the wafer in ways that can later lead to defects and wafer breakage. For example, microcracks may occur during the crystal growth process due to thermal stresses in the silicon crystal. Also, the wafers may be chipped or otherwise damaged by the apparatuses that hold the wafer during and between processing steps. Finally, some processing steps themselves, such as mechanical lapping and grinding, may damage the wafer in ways that can lead to the defect formation, wafer warp or wafer breakage in downstream processes.
To curb the danger of wafer warp or breakage, wafer manufacturing processes generally include various steps for removing damage caused by earlier processing steps. For example, etching and polishing steps generally follow mechanical grinding steps to remove damage caused by the grinding step. Similarly, edge polishing steps are used to remove damage in the edges of the wafers caused by wafer cutting and edge shaping processes.
Though these steps are effective to remove damage that occurs during upstream processing steps, they may be ineffective to lessen the impact of damage that may occur in downstream processing steps. For example, an edge-polishing step that removes damage caused in the wafer cutting step is ineffective to prevent later damage to the edges from propagating. Furthermore, some of the damage-removal steps may expose new surfaces on the wafer that are susceptible to damage. For example, beveling the edge of a wafer to remove wafer-cutting damage typically forms one or more sharp corners on the wafer edge that may be susceptible to chipping or cracking in downstream processes. Edge rounding is superior to edge beveling for preventing downstream damage, but still does not help to alleviate the problems that arise once the wafer edge has been damaged.
Therefore, it would be desirable to have a method of manufacturing a wafer that produces a wafer with improved resistance to breakage and defect propagation caused by downstream processing steps.
SUMMARY OF THE INVENTION
The present invention provides a method of manufacturing a silicon wafer. The method comprises adding polycrystalline silicon to a crucible, adding a nitrogen-containing dopant to the crucible, heating the polycrystalline silicon to form a melt of nitrogen-doped silicon, pulling a nitrogen-doped silicon crystal from the melt using a seed crystal according to the Czochralski technique, forming a silicon wafer from the silicon crystal, the silicon wafer having an edge, and rounding the edge of the silicon wafer. The method may optionally include applying an electrical potential across the crucible while pulling the nitrogen-doped silicon crystal from the melt.
REFERENCES:
patent: 2842467 (1958-07-01), Landauer et al.
patent: 4330359 (1982-05-01), Shlichta
patent: 4548670 (1985-10-01), Pinkhasov
patent: 5357898 (1994-10-01), Kurosawa et al.
patent: 5723337 (1998-03-01), Muller et al.
patent: 5803977 (1998-09-01), Tepman et al.
patent: 5834363 (1998-11-01), Masanori
patent: 5882398 (1999-03-01), Sonokawa et al.
patent: 5911826 (1999-06-01), Hiraishi et al.
patent: 5935320 (1999-08-01), Graef et al.
patent: 5993493 (1999-11-01), Takamizawa et al.
patent: 6001175 (1999-12-01), Maruyama et al.
patent: 6059875 (2000-05-01), Kirkland et al.
patent: 6077343 (2000-06-01), Iida et al.
patent: 6228165 (2001-05-01), Baba et al.
patent: 6261361 (2001-07-01), Iida et al.
patent: 6316361 (2001-11-01), Hansson
patent: 6375749 (2002-04-01), Boydston et al.
patent: 10 47 390 (1958-12-01), None
patent: 0 319 031 (1989-06-01), None
patent: 0 462 741 (1991-12-01), None
patent: 2 198 966 (1988-06-01), None
patent: 62-275087 (1987-11-01), None
patent: WO86/02919 (1984-11-01), None
patent: WO99/57344 (1999-11-01), None
CZ Silicon Crystal Grown in Transverse Magnetic Fields, K. Hoshi et al., Extended Abstracts, vol. 80-1, 1980, pp. 811-813.
Controlling the Oxygen Concentration of Silicon Crystals by Magnetically Induced Melt Rotation, E. M. Hull, IBM Technical Disclosure Bulletin, vol. 23, No. 7A, Dec. 1980.
Semiconductor Silicon Crystal Technology, F. Shimura, Academic Press, Inc., San Diego, CA, 1988, pp. 178-181.
Stanley Wolf and Richard N. Tauber,Silicon Processing For The VLSI Era, vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, USA, pp. 1-72, 124-159, 1986.
Dietze Gerald R.
Hanna Sean G.
Radzimski Zbigniew J.
Alston & Bird LLP
Hiteshew Felisa
SEH America Inc.
LandOfFree
Optimized silicon wafer strength for advanced semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Optimized silicon wafer strength for advanced semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimized silicon wafer strength for advanced semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3061646