Optimized rounding in underflow handlers

Details Optimized rounding in underflow handlers Optimized rounding in underflow handlers

1998-09-30

2001-04-17

Chan, Eddie (Department: 2183)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S497000, C708S498000, C708S551000, C712S222000

Reexamination Certificate

active

06219684

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to computer systems. In particular, the invention relates to rounding in floating-point processors.
2. Description of Related Art
Many modern microprocessors operate on single precision floating point data types. One of the numeric exceptions that can occur during floating-point computations is the underflow exception (UE). The UE can be masked by setting certain control bits in a control register. If the UE is masked, then usually the processor will generate the proper underflowed result.
The masked response consists of producing a denormalized result (if possible, or else a zero is generated) that is rounded according to the rounding mode bits in the control register. Denormalizing a floating-point number (referred to as gradual underflow) consists of gradually shifting the significand to the right and inserting leading zero's with each shift, while decrementing the exponent until the minimum exponent (EMIN), that can be represented in single precision format, is reached. If all non-zero significand bits are shifted out before the EMIN is reached then a zero result is generated. Finally, the denormalized result has to be rounded according to the rounding control bits.
Implementing such a denormalizing process and rounding requires significant amount and hardware. Therefore, it is more desirable to implement this task in the microcode exception handler. Still, the denormalization and rounding emulation in microcode is complicated and consumes a large amount of microcode read only memory (ROM) space and execution time.
Therefore there is a need in the technology to provide a simple and efficient method to perform the rounding process for floating-point numeric data to reduce ROM space and execution time. SUMMARY
The present invention is a method and apparatus for rounding a result operand of a floating-point (FP) operation which causes an underflow. The FP operation is recomputed using a truncate rounding mode to generate an underflowed operand. The underflowed operand is denormalized and providing characteristic bits. A rounding bit is generated based on the characteristic bits. The rounding bit is merged with the denormalized operand to generate the rounded result operand.


REFERENCES:
patent: 4839846 (1989-06-01), Hirose et al.
patent: 5258943 (1993-11-01), Gamez et al.
patent: 5892697 (1999-04-01), Brakefield
patent: 5903479 (1999-05-01), Schwarz et al.
patent: 5943249 (1999-08-01), Handlogten
patent: 6029243 (2000-02-01), Pontius et al.

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