Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
1999-09-21
2002-06-04
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
C438S510000, C438S528000, C438S530000
Reexamination Certificate
active
06399458
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to metal-on-silicon (MOS) structures, and more particularly, to MOS structures that contain a low-resistance diffusion region therein, said low-resistance diffusion region having acceptable defect density, reliability and process control.
BACKGROUND OF THE INVENTION
Bipolar transistors use a relatively highly doped layer in the collector region to reduce the collector resistance and to improve the device performance. This region is called the sub-collector, and it is formed below the other diffusion regions which compose the bipolar transistor. Moreover, it is necessary to form a relatively highly doped reachthrough diffusion under the collector contact which connects the sub-collector to the surface with a relatively low-resistance diffusion. This is well-known, standard bipolar transistor design.
It is also desirable to have a capacitor element available on the same die for use in circuit design, and to reuse as many processing steps as possible that are part of the normal process flow to fabricate the capacitor. One advantage of reusing processing steps to fabricate an MOS capacitor is lower cost. It is imperative that the processes used to fabricate an MOS capacitor provide the desired reliability, defect density necessary for the application, and be sufficiently controllable to yield consistent electrical characteristics from process to process.
In the prior art, the diffusion region can be prepared using two different processes. These prior art processes are illustrated in
FIGS. 1 and 2
. In these figures, reference numeral
10
represents a silicon substrate,
12
represents shallow trench isolation regions,
14
represents an oxide that is formed on the surface of substrate
10
prior to ion implantation,
16
represents a preamorphization region, and
18
represents a diffusion region.
Specifically,
FIGS. 1
a-b
show a diffusion made from a low dose, very shallow antimony (Sb) implant (Sb concentration 1-2×10
14
atoms/cm
2
; ion implant energy 45 KeV), followed by a low energy, high dose phosphorous (P) implant (P concentration 4-6×10
15
atoms/cm
2
; ion implant energy 20 KeV). In this prior art process, the antimony preamorphizes the silicon substrate from the top surface to a peak depth of about 30 nm below the silicon surface. After implanting the diffusion into the silicon wafer, the wafer is annealed and the surface is re-crystallized. The preamorphization step eliminates defects in the Si after anneal. Because the implant is shallow, it was determined that the MOS capacitor oxide that was grown later over this diffusion region was unreliable. Furthermore, this prior art resulted in large variations in the oxide thickness of the oxide grown over this diffusion region due to large variations in surface dopant concentration. Moreover, this prior art technique produced wide variations in oxide thickness among different process runs indicating the silicon oxidation was extremely sensitive to small, normal process variations.
FIG. 2
illustrates a second implantation method that can be employed in the prior art to manufacture a diffusion region. This prior art process is similar to the one shown in
FIGS. 1
a-b
above except that the low energy, low dose Sb implant is eliminated—that is, no preamorphization step is employed. Instead, a single relatively high energy, high dose phosphorous implant is employed. This prior art process corrected the unreliable oxide and variable oxide problems, but dislocations and stacking faults in the silicon are present with this technique after annealing.
In view of the above drawbacks with prior art processes of fabricating diffusion regions, there is a continued need to develop new and improved methods that are capable of forming diffusion regions that have an acceptable defect density, reliability and process control, yet have low-resistance.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a diffusion region having low-resistance (a sheet rho of less than approximately 50.0 ohm/sq.).
Another object of the present invention is to provide a method of fabricating a diffusion region which has acceptable defect density, reliability and process control.
A further object of the present invention is to provide a diffusion region which can be employed in MOS capacitors.
These and other objects and advantages can be obtained by employing the method of the present invention wherein the energy of the high dose dopant, e.g. phosphorous, implant step is selected to keep the peak of implant, Rp, within the amorphous region created by a previously conducted preamorphizing implant step. Specifically, the method of the present invention is used in forming a low-resistance diffusion region in a silicon substrate, said method comprising the steps of:
(a) subjecting a silicon substrate to a first ion implantation step, said first ion implantation step being conducted under conditions such that a region of amorphized Si is formed in said silicon substrate;
(b) subjecting said silicon substrate containing said region of amorphized Si to a second ion implantation step, said second ion implantation step being carried out by implanting a dopant ion into said silicon substrate under conditions such that the peak of implant of said dopant ion is within the region of amorphized Si; and
(c) annealing said silicon substrate under conditions such that said region of amorphized Si is re-crystallized thereby forming a diffusion region in said silicon substrate.
It is noted that the method of the present invention provides diffusion regions that meet the following three criteria: (i) low-resistance; (ii) low Si defects formed during annealing of the implanted Si; and (iii) a reliable oxide region having a uniform thickness with a cross wafer uniformity of approximately ±5%. While prior art processes may satisfy one or even two of these properties, they do not satisfy all of them.
Another aspect of the present invention relates to a method of forming an MOS capacitor which contains the diffusion region of the present invention therein. Specifically, this aspect of the present invention comprises conducting steps (a)-(c) mentioned above and then conducting the following steps:
(d) forming a dielectric layer on said silicon substrate;
(e) forming a doped polysilicon layer on said dielectric layer; and
(f) annealing the doped polysilicon layer to activate the same.
In addition to providing methods of fabrication, the present invention also is directed to structures that are obtained by those methods. In accordance with this aspect of the present invention, an MOS structure is provided which comprises a silicon substrate having a diffusion region formed therein, said diffusion region having a resistance of 50 ohm/sq. or less, and being formed at a depth of from about 500 Å or greater from the surface of said silicon substrate.
When used as an MOS capacitor, the MOS structure further includes a dielectric layer formed on said silicon substrate; and a layer of activated, doped polysilicon on said dielectric layer.
REFERENCES:
patent: 4898839 (1990-02-01), Fujinuma et al.
patent: 4939099 (1990-07-01), Seacrist et al.
patent: 5218228 (1993-06-01), Williams et al.
patent: 5254484 (1993-10-01), Hefner et al.
patent: 5391905 (1995-02-01), Yamazaki
patent: 5414291 (1995-05-01), Miwa et al.
patent: 5576237 (1996-11-01), Bergemont et al.
patent: 5641692 (1997-06-01), Miwa et al.
patent: 5661066 (1997-08-01), Takemoto et al.
patent: 5736776 (1998-04-01), Yamamoto et al.
patent: 6189746 (2001-01-01), Yu
patent: 6184112 (2001-02-01), Maszara et al.
Coolbaugh Douglas D.
Harame David L.
International Business Machines - Corporation
Nguyen Tuan H.
Sabo William D.
Scully Scott Murphy & Presser
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