Optimized power bus structure

Details Optimized power bus structure Optimized power bus structure

1994-12-02

1997-09-16

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

257691, H01L 2710

Patent

active

056683898

ABSTRACT:
An arrangement for providing power to a semiconductor array of cells on a substrate in which the metal 2 power conductors are truncated into short lengths sufficient only to reach between the metal 1 power conductors of adjacent rows of cells, the metal 2 power conductors are placed under the metal 4 power conductors at each side to reduce the current through the metal 3 power conductors, and the metal 3 power conductors are narrowed to the level necessary to carry the reduced current and placed adjacent upper or lower edges of the cells. The arrangement increases the amount of space available for access to the external connection nodes of the devices in the cells of a group on a substrate while reducing the size of the metal overlays necessary to carry power to the cells.

REFERENCES:
patent: 5119169 (1992-06-01), Kozono et al.
patent: 5315130 (1994-05-01), Hively et al.

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