Optimized phase alignment in analog-to-digital conversion of...

Television – Basic receiver with additional function – Multimode

Reexamination Certificate

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C348S572000, C348S537000, C348S520000, C341S155000, C341S172000

Reexamination Certificate

active

07995144

ABSTRACT:
A digital video system (2) is disclosed, in which an analog input video signal is sampled at an optimum sample phase (Pnc), and converted to a digital datastream for display. A phase-locked loop (12) generates a plurality of sample clock phases. One of the sample clock phases (Pnc) is applied to an analog-to-digital converter (10), which digitizes the analog input video signal accordingly. Phase alignment circuitry (20) is provided that includes three sample-and-hold circuits (22b,22c,22a) that sample the analog input video signal, in parallel with the analog-to-digital converter (10), at times before, at, and after the current sample clock phase used by the analog-to-digital converter (10). The earlier and later sampled voltages are compared against the current sampled voltages to generate difference voltages that are each compared against a threshold voltage (Vthr). The numbers of times that the difference voltages exceed the threshold voltage over a field or frame is analyzed according to various techniques, to determine whether and in which direction to adjust the position of the current sample clock phase within the pixel period.

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Xiu et al., “A Method of Automatically Searching the Sampling Frequency and Sampling Phase for Graphic Digitizer in Pixelated Display Applications”, Journal of Imaging Science and Technology, vol. 50, No. 1 (Soc. for Imaging Science and Technology, Jan./Feb. 2006), pp. 80-92.

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