Optimized multiplexer structure for emulation systems

Details Optimized multiplexer structure for emulation systems Optimized multiplexer structure for emulation systems

1995-10-30

1998-01-27

Teska, Kevin J.

Boots, shoes, and leggings

395821, 364238, 364716, 341 85, 341 84, 326105, G06F 1500, H03M 750

Patent

active

057128065

ABSTRACT:
An optimized multiplexer structure reduces the cost in emulation gates in an emulator test system. Extra encoding and decoding logic is added to form a selector with multiple separate subblocks so that the data flow subblock has a reduced input/output (I/O) control path. The circuit reduces the number of control bits from N bits to log.sub.2 N bits.

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