Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-10-30
2003-09-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S017000, C438S018000, C257S048000
Reexamination Certificate
active
06623995
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of monitoring defects in a metal patterning process in the fabrication of integrated circuit devices.
(2) Description of the Prior Art
In the manufacture of large scale integrated circuits, the metal line width or spacing is becoming smaller as technology progresses. As metal lines become thinner, micro-defects start to effect final product output (called C
p
yield) and product reliability. For example, in a 0.15 &mgr;m logic process, micro metal residue has been found between metal lines. This residue is less than 0.2 &mgr;m in size. The residue, found by product failure analysis, kills product reliability. This is known as “infant mortality.” Unfortunately, this type of defect cannot be detected in-line; i.e. during fabrication; because the small size of the residue is out of the resolution limitation of defect scan tools including optical light defect inspection tools such as KLA, AIT, Compass, etc. Furthermore, the conventional Wafer Acceptance Test (WAT) spacing test key cannot catch these micro-defects. It is desired to find a way to detect micro-defects during the fabrication process.
A number of patents address testing issues. For example, U.S. Pat. No. 4,758,094 to Wihl et al. shows a metal monitor for insitu qualification of reticles. U.S. Pat. No. 6,248,661B1 to Chien et al. shows a method for monitoring bubble formation in a spin-on-glass process. U.S. Pat. No. 6,027,859 to Dawson et al. discloses an extended test structure formed in a scribe line. U.S. Pat. No. 5,897,728 to Cole et al. shows a chip attached to a temporary test structure.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide a fast, reliable and very manufacturable method for detecting micro-defects in a metal patterning process in the fabrication of integrated circuit devices.
A further object of the invention is to provide a process for early and effective detection of defects in a metal patterning process.
Another object is to provide a process for fabricating a defect monitor for rapid and effective detection of defects.
Yet another object is to provide a testing structure for early and effective detection of defects in a metal patterning process.
A further object is to provide a testing structure for early and effective detection of defects in a metal patterning process wherein the testing structure has an increased number of test keys and an increased size of test keys.
A still further object of the invention is to provide a process for early and effective detection of defects in a metal patterning process wherein the testing loop can be completed in 30 hours.
Yet another object is to provide a testing structure for early and effective detection of defects in a metal patterning process wherein the testing structure has a dielectric film over the metal layer in order to reduce or eliminate noise in the test.
In accordance with the objects of the invention, a method of fabricating a defect monitor for rapid and effective detection of defects in a metal patterning process is achieved. A plurality of test keys is provided in scribe lines of a control monitor wafer wherein 50 to 400 test keys, for example, are formed on the control monitor wafer and wherein each of the plurality of test keys has an area of between about 1E6 to 1E7 &mgr;m
2
.
Also, in accordance with the objects of the invention, a method of early and effective detection of defects in a metal patterning process is achieved. A test keys structure is provided comprising a plurality of test keys in scribe lines of a control monitor wafer wherein 50 to 400 test keys are formed on the control monitor wafer and wherein each of the plurality of test keys has an area of at between about 1E6 to 1E7 &mgr;m
2
. A metal layer is deposited on the control monitor wafer. A dielectric layer is deposited overlying the metal layer. Thereafter, the control monitor wafer is tested using some of the plurality of test keys.
Also in accordance with the objects of this invention, a method of detecting defects in a metal patterning process is achieved. A test keys structure is provided comprising a plurality of test keys in scribe lines of a control monitor wafer wherein 50 to 400 test keys are formed on the control monitor wafer and wherein each of the plurality of test keys has an area of between about 1E6 to 1E7 &mgr;m
2
. A metal layer is deposited on the control monitor wafer and patterned to form metal lines. A dielectric layer is deposited overlying the metal lines. An opening is etched to one of the metal lines. Thereafter, the control monitor wafer is tested using some of the plurality of test keys.
Also in accordance with the objects of this invention, a test keys structure is achieved. The test keys structure comprises a plurality of test keys in scribe lines of a control monitor wafer wherein between 50 and 400 test keys are formed on the control monitor wafer and wherein each of the plurality of test keys has an area of between about 1E6 and 1E7 &mgr;m
2
.
REFERENCES:
patent: 5576554 (1996-11-01), Hsu
patent: 5843799 (1998-12-01), Hsu et al.
patent: 5872018 (1999-02-01), Lee
patent: 6124143 (2000-09-01), Sugasawara
patent: 6133055 (2000-10-01), Yeh
patent: 6235642 (2001-05-01), Lee et al.
patent: 6521910 (2003-02-01), Lin
Chen Hsien-Tsong
Chen Yu-Chang
Chien Shion-Feng Chang
Hwang Woan Tyng
Wen Tien-Tzu
Ackerman Stephen B
Gurley Lynne A.
Niebling John F.
Pike Rosemary L. S.
Saile George O.
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