Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2002-09-30
2004-10-12
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S208000, C365S049130, C365S051000
Reexamination Certificate
active
06803610
ABSTRACT:
The present invention relates to a method and structure for an improved circuit element physical layout, and more particularly to a physical layout of semiconductor circuit blocks.
BACKGROUND OF THE INVENTION
Conventional content addressable memory (CAM) is implemented primarily using static random access memory (SRAM) cells. SRAM-based CAMs have received widespread use due to the high access speed and static nature of SRAM memory cells. Furthermore, SRAM cells can be manufactured using a pure-logic type fabrication process, which is commonly used for non-memory circuit blocks.
While they have random access memory (RAM) functionality of storing data, CAMs are predominantly used for searching. The search data is compared with stored data in order to determine if the stored data matches search data applied to the memory. When newly applied search data matches data stored in the memory, a match result is indicated. If the searched and stored data do not match, a mismatch result is indicated. CAMs are particularly useful for fully associative memories such as look-up tables and memory-management units.
Many current applications utilise ternary CAMS, which are capable of storing three logic states. For example, three logic states are logic ‘0’, logic ‘1’ and “don't care”. Therefore, such CAM cells require two memory cells to store the logic states as well as a comparison circuit for comparing stored data with search data provided to the CAM.
In ternary form, each conventional SRAM-based CAM memory cell comprises a typical six-transistor (6T) SRAM cell. That is, each SRAM cell requires 2 p-channel transistors and 2 n-channel transistors in a cross-coupled inverter relationship and a further 2 n-channel transistors as access devices to associated bit lines. Therefore, an SRAM-based ternary CAM cell typically consists of 12 transistors to implement the two 6T SRAM cells. Furthermore, four additional transistors are required for each ternary CAM memory cell for implementing an exclusive-NOR function for comparing the search data with the stored data.
When implementing a physical, device-level layout of an SRAM-based CAM cell circuit in semiconductor material, the main goal is to minimize physical area occupied by each cell while maintaining optimal circuit design functionality and performance. It is the task of the physical layout designer to create the smallest cell layout possible while satisfying both the integrated circuit (IC) manufacture's layout design rules and the circuit designer's specifications. As the cell layout is repeated numerous times to create a memory array, even a small reduction in the cell size results, cumulatively, in a significant reduction in overall die size and power consumption.
It is recognized that a factor in improving the performance of the CAM, is to share common circuit nodes, such as a matchline node, between neighboring cells. Sharing the matchline node contact between adjacent cells, for example, minimizes the area taken by each cell as well as reduces the overall parasitic capacitance of the matchline, since the number of contacts per matchline is reduced.
For clarity, throughout this document, the term “tiling” refers to maintaining the same orientation of a cell as it is repeated in a two dimensional array. The term “mirroring” refers to flipping the cell along a vertical or horizontal axis for each subsequent instantiation of the cell in the array.
In the past, CAM cells have been laid out with shared nodes on a boundary between neighbouring cells. Practical layouts generally tend to share as many nodes as possible in order to reduce area and signal line parasitic capacitance. Some nodes must be shared by mirroring the cell along an axis, while other nodes, such as power nodes, can be shared by either mirroring or tiling cells along an axis. As an example, a power node may be shared between four cells when placed at an intersection of two axes. Accordingly, efficient CAM cell designs make effective use of these contact-sharing techniques.
Often when utilizing contact or node sharing techniques, a decision between tiling and mirroring along a vertical and horizontal axis must be made. The positive and negative aspects of each option must be considered before deciding on a solution. For example, mirroring may allow for more sharing, but may crowd internal connections in the cell layout, thus requiring an increase in the size of the cell along its perpendicular axis. Conversely, tiling may not allow as much node sharing to occur as in a mirrored layout approach, but tiling will most likely not result in crowded internal connections in the cell layout, thus allowing for a smaller cell size.
Using the techniques applied in the art rarely results in an optimum solution since in each case a negative aspect compliments each positive aspect. While many conventional approaches effectively reduce cell size, there is still room for further improvement. Thus, it is an object of the present invention to further improve cell size while maintaining common node sharing between cells.
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention there is provided a semiconductor circuit array having a plurality of memory cells. Each of the memory cells includes a first, a second, a third and a fourth segments. The first and second segments form a first half of a memory cell and the third and fourth segments form a second half of a memory cell. The third segment is a mirror image of the first segment, and the fourth segment is a tiled image of the second segment.
The present invention seeks to provide a cell that achieves maximum performance with minimum size.
An advantage of the present invention is to provide a layout of CAM cells that optimizes node sharing while reducing the die size of the cell.
A further advantage of the present invention is to provide a layout that optimizes node sharing, reduces the die size of the cell, and complies with the layout design rules.
Yet a further advantage of the present invention is to provide a cell layout that reduces parasitic capacitance, resistance and leakage current.
REFERENCES:
patent: 6563727 (2003-05-01), Roth et al.
Dunn Matthew
Koolhaas Martin
Cramer Owen
Mosaid Technologies Incorporated
Pillay Kevin
Tran Minhloan
Tran Tan
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