Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-01-21
2001-09-04
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S437000, C327S576000
Reexamination Certificate
active
06285247
ABSTRACT:
FIELD OF INVENTION
This invention is in the field of Complementary Symmetry Metal Oxide Field Effect transistors (CMOS) digital integrated circuit structures and operation thereof.
BACKGROUND OF THE INVENTION
Complementary symmetry Metal Oxide Semiconductor (CMOS) structures for digital operation have arisen from the need to reduce power consumption during quiescent, OFF times while preserving high clock operating frequencies. The advantage of CMOS over other structures, in general, is that power is consumed only during transition times when individual Metal Oxide Semiconductor Field Effect Transistors (MOSFET) forming a CMOS pair switch from ON to OFF or from OFF to ON. Whenever a CMOS pair is either in the ON or OFF state, and not in a switching state, power dissipation is nominally zero. Thus, CMOS is well suited for digital operation where individual CMOS pairs forming, for example, a microprocessor logic circuit FETs may be in either the ON of OFF state for extended periods of time as part of normal operation.
While power dissipation may be negligible during either the ON or OFF steady state, CMOS pairs switching at hundreds of megahertz during normal circuit operation dissipate substantial power. This dissipation becomes of concern as the number of CMOS pairs per unit area of a substrate increase, as exemplified by shrinking circuit geometries approaching 0.1 micron. Thus, the combination of high pair density per unit area with increased switching speeds has typically forced the reduction of operating voltage for viable operation.
The prior art suggests reduction in power dissipation of dense CMOS circuits by unlimited reduction of the voltage supplied to the CMOS. Reduction in V
DD
, the voltage supplied to the CMOS integrated circuit is exemplified by the history of voltage reductions made in accordance with circuit density. V
DD
has gone from the customary 5 volts, followed by 3.3 volts, then 1.8 volts, as exemplified by Texas Instrument's TMS320C67X line of processors. Other processors, operating at about 60 Mhz, operate at 0.9 volts to further reduce dynamic power dissipation. Some battery operated systems operate at a V
DD
of 1.6 volts.
The concept of voltage reduction for reducing power dissipation in the prior art, is exemplified in CMOS Circuit Design, Layout, and Simulation, By R. Jacob Baker, Harry W. Li and David E. Boyce, IEEE Press, ISBN 0-7803-3416-7. In this reference, section 11.2.2 suggests that dynamic power dissipation in a CMOS inverter is a function of the capacitance of the load driven by the inverter and the power supply voltage V
DD
. Thus power dissipation comes from the current flow associated with the charge and discharge of the capacitive load imposed on the output of the inverter. Since a capacitive load requires ½CV
DD
2
of energy to be charged and discharged, the prior art teaches that a reduction in CMOS operating voltage V
DD
will reduce dynamic power dissipation by a factor of V
DD
2
. Furthermore, if a power delay product is to be used to characterize the speed of a digital process, only the switching delay from low to high and high to low is to be considered in conjunction with the average power as discussed in the same reference at equation 11.19.
Thus, the prior art has been teaching to reduce power supply voltage indefinitely for increased CMOS operating clock speed and increased pair density per unit area.
SUMMARY OF THE INVENTION
However, teaching away from the prior art, this invention shows that V
DD
cannot be lowered beneficially indefinitely below an optimal level.
The problem of operating CMOS integrated circuits at a reduced voltage are avoided in accordance with one aspect of the invention by operating a CMOS inverter at an optimal voltage. A digital system of this invention comprises a plurality of P-channel metal oxide semiconductor field effect transistors and a plurality of N-channel metal oxide semiconductor field effect transistors. The P-channel transistors have a PFET conduction threshold voltage. The N-channel transistors have an NFET conduction threshold voltage. The NFET and PFET threshold voltages are determined by extrapolation from the high gate to source voltage. Each of the N-channel transistors are paired with a P-channel transistor. The pairing is arranged in complementary symmetry (CMOS). A power supply connected across one of the pair formed from N-channel and P-channel transistors arranged in complementary symmetry is set to a voltage approximating the sum of the PFET conduction threshold voltage and the NFET conduction threshold voltage. This voltage is other than 5 volts, 3.3 volts, 1.8 volts and 0.9 volts.
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Theory of CMOS digital Circuits and circuit Failures , by M. Shoji, Chapter 5—pp. 1 to 69 inclusive, 1992, Princeton University Press.
CMOS circuit Design, Layout and Simulation, By R. Jacob Baker, Harry W. Li, David E. Boyce, IEEE press, ISBN 0-7803-3416-7—section 11.2.2, pp. 210-212 inclusive, pp. 96-100, Bsim modelling, pp. 107-119, 1998.
Agere Systems Guardian Corporation
Callahan Timothy P.
Englund Terry L.
Istrate Iomescu Jumbepatent.com
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