Optimized layout for multi-bit memory banks each with two...

Details Optimized layout for multi-bit memory banks each with two... Optimized layout for multi-bit memory banks each with two...

2007-06-19

2007-06-19

Dinh, Son (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S063000, C365S185110, C365S230030

Reexamination Certificate

active

10503619

ABSTRACT:
A flash memory1based on the multilevel storage technology for storing the information of two or more bits is provided with four banks2ato2d. For example, in the left side of the bank2a, a data latch6ais provided along one short side of the bank2a, while in the right side thereof, a data latch6bis provided along the other short side of the bank2a. At the lower side of the data latches6a, 6b, arithmetic circuits7a, 7bare provided. The data latches6a, 6bare respectively formed of SRAMs. A sense latch5ais divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch5ais connected with the data latches6a, 6bvia the signal lines respectively allocated along both short sides of the bank2a.

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