Optimized hardware compression and decompression architecture fo

Details Optimized hardware compression and decompression architecture fo Optimized hardware compression and decompression architecture fo

1995-09-15

1998-03-17

Coles, Sr., Edward L.

395112, 395115, G06K 1500

Patent

active

057296685

ABSTRACT:
There is provided an apparatus for compressing data. The apparatus is constructed from a random access memory (RAM). Next, there is an input controller connected to the RAM. A compression unit and decompression unit are connected to the input controller. There is an output controller connected to the compression and decompression units and the RAM. Finally there is a controller connected to the RAM, the input and output controllers.The controller configures the input controller to retrieve input data from the RAM and transfers the retrieved data to an active unit, the active unit being the compression unit for compressing the original data into the compressed data or the decompression unit for decompressing the compressed data into the original data. Under direction of the controller, the output controller retrieves data from the active unit. Data from the output controller may be transferred to the RAM, to a printer, or just counted to determine the size of the data. Either input or output controller may independently be stopped. After the input or output controller is stopped, the controller may reconfigure the input controller or the output controller.

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