Optimized floating P+ region photodiode for a CMOS...

Details Optimized floating P+ region photodiode for a CMOS... Optimized floating P+ region photodiode for a CMOS...

1999-11-15

2002-01-15

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S233000, C257S291000, C438S048000, C438S309000

Reexamination Certificate

active

06339248

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to image sensing devices, and more particularly, to a pixel sensor cell.
BACKGROUND OF THE INVENTION
Integrated circuit technology has revolutionized various fields, including computers, control systems, telecommunications, and imaging. In the field of imaging, the charge coupled device (CCD) has been made popular by its manufacturing and performance characteristics, including its relatively low cost and small size. Nevertheless, the solid state CCD integrated circuits needed for imaging are relatively difficult to manufacture, and therefore are expensive. In addition, because of the differing processes involved in the manufacture of the CCD integrated circuits relative to MOS integrated circuits, the signal processing portion of the imaging sensor has typically been located on a separate integrated chip. Thus, a CCD imaging device includes at least two integrated circuits: one for the CCD sensor and one for the signal processing logic.
Another class of image sensors are the active pixel sensors. As noted in U.S. Pat. No. 5,625,210 to Lee et al. (“the '210 patent), an active pixel sensor refers to an electronic image sensor with active devices, such as transistors, that are associated with each pixel. The active pixel sensor has the advantage of being able to incorporate both signal processing and sensing circuitry within the same integrated circuit. Conventional active pixel sensors typically employ polysilicon photocapacitors or photodiodes as the image sensing elements.
The most popular active pixel sensor structure consists of three transistors and a N+/Pwell photodiode, which is a structure that is compatible with the standard CMOS fabrication process. Examples of other structures are shown in U.S. Pat. No. 5,587,596 (showing a one transistor cell), U.S. Pat. No. 5,926,214 (showing an N-transistor cell), and U.S. Pat. No. 5,933,190 (showing a log scale sensor). In such sensors, desirable characteristics include the ability for the device to have high sensitivity, combined with a low dark current (i.e., the current that is output from the sensor in a dark environment). In the design of active pixel sensors, it is known that for the same sensor size, a deeper junction photodiode will have a higher sensitivity than that of a shallow junction (such as in a typical N+/Pwell). However, the production of such devices usually requires modifications to the standard CMOS fabrication process, and in addition may increase dark current due to larger effective junction areas (when considered from a three-dimensional perspective).
Thus, two of the presently available alternatives are to either use the standard three-transistor plus N+/Pwell photodiode structure that can be formed with the standard CMOS fabrication process, or else abandon the standard CMOS fabrication process in favor of designs that are intended to improve the sensitivity and dark current characteristics. One active pixel sensor design that is not fabricated using the standard CMOS fabrication process is the pinned photodiode, as taught in the '210 patent.
The pinned photodiode has gained favor for its ability to have good color response for blue light, as well as advantages in dark current density and image lag. Reduction in dark current is accomplished by pinning the diode surface potential to the Pwell or Psubstrate (GND) through a P+ region. While the '210 patent provides a method for using a pinned photodiode and an active pixel sensor, the design taught suffers from the drawback of manufacturing complexity. In particular, as seen in the diagrams of the '210 patent, the manufacture of such an apparatus requires multiple masking and photolithography steps.
An improvement over the device taught in the '210 patent is shown in U.S. Pat. No. 5,880,495 to Chen (the '495 patent), which is hereby incorporated by reference. The '495 patent teaches an active pixel pinned photodiode structure that can be made with one less mask than the structure taught in the '210 patent. This is accomplished by removing the need for an N
−
channel underneath the transfer gate as shown in the '210 patent. Instead, a highly doped N
+
well (a “transfer well”) adjacent to the transfer gate is formed that aids in the transfer of charge (the photo signal) from the pinned photodiode to the output circuitry. In addition, the masking steps shown in the '210 patent to form the lightly doped N
−
channel must be precisely aligned to be underneath the transfer gate. In contrast, the alignment of the mask in the '495 device is relatively robust to misalignment.
Even with the improved structure taught in the '495 patent, the pinned photodiode configuration still has certain drawbacks. For example, in a pinned photodiode structure there are four transistors, so the fill factor is smaller for the same area, which results in less sensitivity. In addition, the fabrication process for such a configuration requires significant modification from the standard CMOS fabrication process, due to the buried channel TG transistor. As also noted with reference to the '210 patent, the pinned photodiode configuration may cause image lag due to the incomplete transfer of charge from the diode to the floating node, if the junction profile is not perfectly optimized for the charge transfer.
Thus, what is needed, is a pixel photodiode structure that can be formed utilizing the standard CMOS process, while having a high sensitivity and low dark current.
SUMMARY OF THE INVENTION
A pixel sensor for use in an imaging array and formed in a semiconductor substrate having a first conductivity-type is disclosed. In accordance with one aspect of the invention, the pixel sensor includes a photodiode which is constructed with a P+/Nwell/Psub structure.
The Nwell/Psub junction acts as a deep junction photodiode which offers high sensitivity. The P+ region passivates the silicon surface to reduce dark current. Unlike a pinned photodiode structure, the P+ region in the present invention is not connected to the Pwell or Psub layers, thus making the P+ region floating. This avoids the addition of extra capacitance to the cell. When a contact is made to the diode, the performance may be improved by making sure that the P+ in the contact area is blocked to ensure that it is floating, while also making sure that the N+ is present to ensure good contact to the Nwell.
In accordance with another aspect of the invention, the photodiode is implemented as an active pixel sensor cell, then entire layout of which is compatible with the standard CMOS fabrication process. In addition, this active pixel sensor cell device can be formed utilizing the standard three transistor cell, as opposed to the four transistor cell required for the pinned photodiodes. Alternatively, other configurations may also be used with the photodiode, such as a passive pixel, a two transistor, a four transistor, or a log scale cell.
In accordance with another aspect of the invention, the three transistor active pixel sensor cell includes a reset transistor formed in a semiconductor substrate next to the photodiode, as well as a buffer transistor and a row select transistor. To form the reset transistor, a Pwell is formed in a semiconductor substrate next to the Nwell of the photodiode. Thereafter, a gate is formed over the Pwell, and the source and drain N+ regions are also formed. The drain N+ region is formed over the Pwell, whereas the source N+ region is formed over part of the junction between the Nwell and the Pwell. A field oxide isolation region (e.g., LOCOS isolation) is formed on either side of the Nwell and the Pwell.
In accordance with another aspect of the invention, an additional N type region can be introduced in between the P+ region and Nwell to fine-tune the junction profile for special applications.
In accordance with another aspect of the invention, another variation to the structure is to have the P&pl

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