Optimized FIFO memory

Details Optimized FIFO memory Optimized FIFO memory

1997-09-19

1999-10-12

Chauhan, U.

Computer graphics processing and selective visual display system

Computer graphic processing system

Graphic command processing

345197, 345520, 712207, 712218, G06F 1500, G06T 100

Patent

active

059661429

ABSTRACT:
A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes an XY address for rendering the graphics primitives. A graphics processor, which includes a bypass logic circuit, enables the graphics processor to temporarily store display list commands in an internal storage device while previously fetched display list data is being processed. The bypass logic circuit allows the graphics processor to bypass the internal storage device and write fetched command directly to an execution unit in the graphics processor. By having the bypass capabilities, the graphics processor is able to optimize the internal storing of commands in the display list in the internal storage unit.

REFERENCES:
patent: 5689720 (1997-11-01), Nguyen et al.
patent: 5793386 (1998-08-01), Larson et al.
patent: 5796413 (1998-08-01), Shipp et al.
patent: 5829054 (1998-10-01), Ehlig et al.

Affiliated with

Also associated with

Rating

Optimized FIFO memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optimized FIFO memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimized FIFO memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-657079