Optimized electrically erasable PLA cell for minimum read distur

Details Optimized electrically erasable PLA cell for minimum read distur Optimized electrically erasable PLA cell for minimum read distur

1988-06-15

1991-04-02

Gossage, Glenn

Static information storage and retrieval

Floating gate

Particular biasing

36518908, 357 235, G11C 1604

Patent

active

050051555

ABSTRACT:
A four device cell for an electrically erasable programmable logic device includes a floating gate tunnel device (sometimes referred to as a tunnel capacitor), a floating gate read transistor having its floating gate and control gate connected respectively to the floating gate and control gate of the tunnel capacitor, a read select transistor for selectively coupling the drain of the floating gate read transistor to a product term output in response to an input term, and a write select transistor for selectively coupling the drain of the floating gate tunnel capacitor to a write data line in response to the signal on a write select line. During sensing, the control gates of all the floating gate tunnel capacitors are kept at a constant voltage V.sub.cg. The drains of all of the floating gate tunnel capacitors are also kept at a constant voltage V.sub.WDL chosen to minimize read disturb on the tunnel capacitor. Preferably V.sub.WDL =V.sub.cg. V.sub.WDL is applied to the drain of the floating gate tunnel capacitor by applying V.sub.WDL to all the write data lines and applying at least V.sub.WDL +V.sub.T (where V.sub. T is a select transistor threshold voltage) to all the write select lines of the array.

REFERENCES:
patent: 4402064 (1983-08-01), Arakawa
patent: 4546454 (1985-10-01), Gupta
patent: 4628487 (1986-12-01), Smayling
patent: 4654825 (1987-03-01), Rinerson
patent: 4663740 (1987-05-01), Ebel
patent: 4695979 (1987-09-01), Tuvell et al.
patent: 4715014 (1987-12-01), Tuvell et al.
patent: 4788663 (1988-11-01), Tanaka et al.
patent: 4912534 (1990-03-01), Tanaka et al.
Advanced Micro Devices, Inc., AmPAL22V10 data sheet (10/86).
Johnson, Kuhn, Renninger and Perlegos, "16-K EE-PROM Relies on Tunneling for Byte-Erasable Program Storage", Electronics (2/28/80), pp. 113-117.
Euzent, Boruta, Lee and Jenq, "Reliability Aspects of a Floating Gate E.sup.2 PROM", Intel Corp. Application Note AP-100 (1981).
"A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", K. C. Hardee and R. Sud, IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981, pp. 435-443.
"A 25-ns 16K CMOS PROM Using a Four-Transistor Cell and Differential Design Techniques", S. Pathak, J. Kupec, C. Murphy, D. Sawtelle, R. Shrivastava and F. Jenne, IEEE Journal of Solid-State Circuits, Vo, SC-20, No. 5, Oct. 1985, pp. 964-970.
Session XIII: Nonvolatile Memories, THPM 13.1: "A 25ns 16K CMOS RPOM Using a 4-Transistor Cell", S. Pathak et al., ISSCC 1985, Thursday, Feb. 14, 1985, pp. 162-163, 332.

Affiliated with

Also associated with

Rating

Optimized electrically erasable PLA cell for minimum read distur does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optimized electrically erasable PLA cell for minimum read distur, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimized electrically erasable PLA cell for minimum read distur will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-331001