Optimized electrically erasable cell for minimum read disturb an

Details Optimized electrically erasable cell for minimum read disturb an Optimized electrically erasable cell for minimum read disturb an

1990-10-26

1992-03-31

Gossage, Glenn

Static information storage and retrieval

Floating gate

Particular biasing

36518909, G11C 1604, G11C 1606

Patent

active

051013789

ABSTRACT:
A non-volatile memory apparatus having a plurality of memory cells, each memory cell including a floating gate tunnel device (130) having a drain (134) and a floating gate read transistor (140) having a source (142) and a drain (144), the tunnel device and read transistor in each respective cell having a common floating gate (138, 148) and a common control gate (136, 146). The apparatus includes writing circuitry (102, 160) for writing desired charge levels to the floating gate of a cell to be written during a writing operation, sense circuitry (140, 150) for sensing the charge levels on the floating gate of a cell to be read during a sense operation, and circuitry for applying during the sense operation a predetermined reference voltage to the source of the read transistor in the cell to be read, and a predetermined sense mode drain voltage different from the reference voltage to the drain of the tunnel device in the cell to be read, independently of the voltage at the drain of the read transistor in the cell to be read.

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Pathak et al., "A 25-ns 16K CMOS PROM Using a Four Transistor Cell and Differential Design Techniques", IEEE Jour. of Sol. St. Ccts., vol. SC-20, No. 5, Oct. 1985, pp. 964-970.
Pathak et al., "A 25-ns 16K CMOS PROM Using a Four Transistor Cell", IEEE ISSCC, Feb. 1985, pp. 162-163, 332.
Advanced Micro Devices, Inc., Am PAL22V10 Data Sheet, Oct. 1986.

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