Optimized E.sup.2 pal cell for minimum read disturb

Details Optimized E.sup.2 pal cell for minimum read disturb Optimized E.sup.2 pal cell for minimum read disturb

1989-06-16

1990-06-19

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307465, 365185, G11C 1140

Patent

active

049356488

ABSTRACT:
A four device cell is disclosed for an electrically erasable programmable logic device. The four devices include a floating gate tunnel capacitor, a floating gate read transistor having its floating gate and control gate connected respectively to the floating gate and control gate of the tunnel capacitor, a read select transistor for selectively coupling the drain of the floating gate read transistor to a product term output in response to an input term, and a write select transistor for selectively coupling the drain of the floating gate tunnel capacitor to a write data line in response to the signal on a write select line. During sensing, the control gates of all the floating gate tunnel capacitors are kept at a constant voltage V.sub.cg. The drains of all of the floating gate tunnel capacitors are also kept at a constant voltage V.sub.WDL chosen to minimize read disturb on the tunnel capacitor. Preferably V.sub.WDL =V.sub.cg .multidot.V.sub.WDL is applied to the drain of the floating gate tunnel capacitor by applying V.sub.WDL to all the write data lines and applying at least V.sub.WDL +V.sub.T to all the write select lines of the array.

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