Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2006-04-11
2006-04-11
Malzahn, D. H. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07028064
ABSTRACT:
An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.
REFERENCES:
patent: 4156920 (1979-05-01), Winograd
patent: 4604721 (1986-08-01), Gray
patent: 6351759 (2002-02-01), Moretti
Becker Peter
Buchert Ryan Samuel
Shahrier Sharif M.
InterDigital Technology Corporation
Malzahn D. H.
Volpe and Koenig P.C.
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