Optimized decoupling capacitor using lithographic dummy filler

Details Optimized decoupling capacitor using lithographic dummy filler Optimized decoupling capacitor using lithographic dummy filler

1999-11-18

2001-05-15

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

C257S401000

Reexamination Certificate

active

06232154

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the formation of capacitors in semiconductor circuits, and more specifically to the utilization of unused “dummy” border areas of the DRAM arrays as decoupling capacitors and other useful structures in logic and memory arrays.
2. Description of the Related Art
In order to minimize noise effects, decoupling capacitors are often needed in very large scale integration (VLSI) circuits, to be attached in the various type of power supplies of logic and memory array circuits. Whether externally provided or internally generated, power supply voltage levels on advanced DRAM arrays, may typically vary from −0.5V to about 3.5V, which makes it difficult to implement sufficient decoupling capacitors for all types of power supplies. For example, voltages such as the boosted wordline voltage, are too high to be applied on a deep trench decoupling capacitor where reliability of the dielectric is a key concern. Moreover, such capacitors require a large amount of chip area which makes it difficult to find space on the chip to provide enough decoupling capacitors for each power supply.
VLSI circuits, especially memory arrays, have uniform repeatable shape patterns which are formed by lithographic techniques. However, due to different pattern densities, the patterns along the edges of the array are slightly different than the patterns not located along the edge (e.g., the “edge” effect). For example, elements such as via contacts that are located near the edge of the array often have patterns after exposure which are smaller than those located in the middle of the array due to uneven pattern density.
To overcome this problem, a few columns of “dummy” patterns are formed at the edge of the array. Therefore, there are no active devices located at the edge of the array and all active devices will have uniformly-patterned shapes. The dummy patterns formed along the edge of the array are normally tied to a certain voltage level (e.g., GND/Vdd) and are not used. For large arrays, the area wasted by dummy patterns can be significant.
The invention utilizes the otherwise wasted areas to simultaneously satisfy the uniform pattern density for better lithographic patterning and optimize the size and filling of the decoupling capacitors regardless of different power supplies, which in turn increases the overall effective utilization of the chip.
SUMMARY OF THE INVENTION
The present invention addresses the above problem with a method comprising the acts of performing a partial topographical layout of a semiconductor chip, the partial topographical layout including a plurality of power-supply nets; identifying an area not occupied by the partial topographical layout; selecting a power-supply net in the plurality of power-supply nets, depending on a spacial relationship between the plurality of power-supply nets and the area; augmenting the partial topographical layout, by assigning a capacitor to the area and making a connection between the selected power-supply net and the capacitor.


REFERENCES:
patent: 5361234 (1994-11-01), Iwasa
patent: 5998846 (1999-12-01), Jan et al.

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