Optimized CPU-memory high bandwidth multibus structure...

Details Optimized CPU-memory high bandwidth multibus structure... Optimized CPU-memory high bandwidth multibus structure...

1998-05-14

2002-04-23

Yao, Kwang Bin (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C710S120000

Reexamination Certificate

active

06377581

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the field of computer systems. More specifically, the present invention relates to the field of interconnecting the internal components and peripheral devices of a computer system.
BACKGROUND ART
A computer system can be fabricated from a wide variety of individual components and devices which enable it to operate and perform many desirable functions. Some of the internal components of a computer system can include a central processing unit (CPU), a computer readable volatile memory unit (e.g., random access memory, static RAM, dynamic RAM, etc.), a computer readable non-volatile memory unit (e.g., read only memory, programmable ROM, flash memory, EPROM, EEPROM, etc.), a computer readable mass data storage device such as a magnetic or optical disk, modem device, graphics hardware, sound hardware, and the like. Furthermore, some of the peripheral devices of a computer system, which increase its overall functionality, can include a display device, a keyboard for inputting alphanumeric characters, a cursor control device (e.g., mouse), a printer, a scanner, speakers, and the like. Of all the many and diverse components and devices that constitute a computer system, the CPU is its most important functional component. The CPU is made up of circuitry which receives and interprets instructions and then controls their execution within itself or within the other internal components and peripheral devices of the computer system. As such, the CPU is the “brain” of the entire computer system.
Since the CPU is so critical to the operation of the other internal components and peripheral devices of the computer system, it is necessary to couple the CPU to these various components. Within the prior art, there are differing techniques for coupling the CPU to the various components that constitute the computer system. One of these prior art techniques utilizes an integrated circuit (IC) chip, commonly referred to as a North Bridge chip, as an interface between the CPU and the remaining components. Typically, a North Bridge chip is designed and fabricated to enable the various buses of the computer system to intercommunicate, thereby enabling the CPU to communicate with the various internal components and peripheral devices coupled to the buses of the computer system. Furthermore, a North Bridge chip also enables intercommunication between the various components and devices of the computer system.
FIG. 1
is a block diagram of an example of a prior art North Bridge chip
100
used to interconnect buses
114
-
120
within a computer system, thereby enabling intercommunication between the internal components and peripheral devices of the computer system. In order to implement intercommunication between the computer system components, North Bridge chip
100
is substantially comprised of interface circuitry modules
102
-
110
, which enable intercommunication between buses
114
-
120
of the computer system. In other words, CPU slave interface
102
, CPU master interface
104
, AGP interface
106
, PCI interface
110
, and memory interface
108
enable intercommunication between memory bus
114
, peripheral component interconnect (PCI) bus
116
, accelerated graphics port (AGP) bus
118
, and CPU bus
120
. It should be appreciated that interface modules
102
-
110
of North Bridge chip
100
are interconnected to each other by point-to-point buses, which are represented in
FIG. 1
by the arrows that interconnect them. Typically, any two modules of North Bridge chip
100
that can potentially communicate are connected by point-to-point buses.
There are some disadvantages associated with the prior art technique of utilizing a North Bridge chip to couple a CPU to the remaining components that comprise a computer system. One of the disadvantages is that each North Bridge chip is designed and fabricated specifically to operate within a particular computer system. As such, North Bridge chips ordinarily cannot be utilized within other computer systems for which they are not designed. In other words, North Bridge chips are not generally interchangeable. Therefore, each time significant modifications are implemented within an existing or future computer system, a substantial amount of circuitry within an existing North Bridge chip typically has to be redesigned from scratch in order to accommodate the significant modifications. These significant computer system modifications can, for example, include using a different CPU family (e.g., Intel, Motorola, etc.), using a CPU having a different operating frequency, using different memory technology, using a CPU to memory bus having a different width, or adding a new module (e.g., interface or functional) to the existing design of a North Bridge chip. It should be appreciated that the of redesigning North Bridge chips would be less problematic if they were small in size. But ordinarily, North Bridge chips are significant in size. Consequently, redesigning and fabricating a North Bridge chip essentially from scratch consumes significant amounts of design time, thereby detrimentally increasing manufacturing costs.
One of the prior art practices used to reduce the amount of time required to design or redesign a North Bridge chip is to make each point-to-point bus that interconnects the individual modules all identical technology, thereby reducing the amount of unique bus technologies within the North Bridge chip and simplifying the overall design. But there are some disadvantages associated with this prior art practice. Typically, the point-to-point bus technology duplicated throughout a North Bridge chip is the CPU to memory point-to-point bus technology, which is usually the leading bus technology having the maximum data bandwidth requirement. However, some of the modules (e.g., PCI interface module) located within the North Bridge chip normally are unable to take advantage of these maximum bandwidth point-to-point buses because their particular bandwidth requirement is fixed. As such, these maximum bandwidth buses needlessly consume more silicon area within the North Bridge chip as required by the circuitry and in some circumstances also consume additional power. These are some of the disadvantages associated with the prior art practice of duplicating the maximum bandwidth point-to-point bus technology throughout a North Bridge chip.
Another disadvantage associated with the prior art technique of utilizing a North Bridge chip to interconnect a computer system is that there are physical limitations to the amount of point-to-point buses which can be implemented within the North Bridge chip. It should be appreciated that this disadvantage does not become problematic when the number of modules within a North Bridge chip are few. However, over time computer manufacturers continue to add more and more functionality to their computer systems. As such, the North Bridge chips within these computer systems are implemented with more and more functionality, causing them to become increasingly complex. Consequently, the number of interface and/or functional modules of the North Bridge chip continues to increase, thereby increasing the number of point-to-point buses which interconnect the modules. Eventually, a point is reached physically where it becomes almost impossible to route any more buses within the North Bridge chips because there are too many wires within it.
Therefore, it would be advantageous to provide a system to interconnect the internal components and peripheral devices of a computer system which is substantially reusable when significant modifications are subsequently implemented within future computer systems. Furthermore, it would also be advantageous for this same system not to become overly complex and/or excessively large when significant modifications are later implemented within future computer systems. The present invention provides these advantages.
DISCLOSURE OF THE INVENTION
The present invention includes a system which communicatively couples the internal components (e.g., CPU, memory, etc.) and p

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