Optimized circuits for three dimensional packaging and...

Amplifiers – With control of power supply or bias voltage

Reexamination Certificate

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Details

C330S126000, C330S250000, C455S333000, C455S334000, C455S341000, C257S499000, C257S500000, C438S006000, C438S026000

Reexamination Certificate

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07471146

ABSTRACT:
An embodiment of the present invention provides an apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a top tier substrate and a second portion of the integrated circuit is placed on a bottom tier substrate stacked adjacent the top tier substrate and wherein the first portion and the second portion of the integrated circuit are interconnected; and printed spiral arms stacked vertically on both the top and bottom surface of the top tier substrate thereby creating high Q inductors.

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Gordon Gray, “Enabling Cost Effective Integration Through Package Stacking”, Jan. 17-19, 2006, IWPC.

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