Amplifiers – With control of power supply or bias voltage
Reexamination Certificate
2006-02-14
2008-12-30
Chiang, Jack (Department: 2825)
Amplifiers
With control of power supply or bias voltage
C330S126000, C330S250000, C455S333000, C455S334000, C455S341000, C257S499000, C257S500000, C438S006000, C438S026000
Reexamination Certificate
active
07471146
ABSTRACT:
An embodiment of the present invention provides an apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a top tier substrate and a second portion of the integrated circuit is placed on a bottom tier substrate stacked adjacent the top tier substrate and wherein the first portion and the second portion of the integrated circuit are interconnected; and printed spiral arms stacked vertically on both the top and bottom surface of the top tier substrate thereby creating high Q inductors.
REFERENCES:
patent: 5312790 (1994-05-01), Sengupta et al.
patent: 5427988 (1995-06-01), Sengupta et al.
patent: 5486491 (1996-01-01), Sengupta et al.
patent: 5593495 (1997-01-01), Masuda et al.
patent: 5635433 (1997-06-01), Sengupta
patent: 5635434 (1997-06-01), Sengupta
patent: 5640042 (1997-06-01), Koscica et al.
patent: 5693429 (1997-12-01), Sengupat et al.
patent: 5694134 (1997-12-01), Barnes
patent: 5766697 (1998-06-01), Sengupta et al.
patent: 5830591 (1998-11-01), Sengupta et al.
patent: 5846893 (1998-12-01), Sengupta et al.
patent: 5886867 (1999-03-01), Chivukula et al.
patent: 5990766 (1999-11-01), Zhang et al.
patent: 6074971 (2000-06-01), Chiu et al.
patent: 6377142 (2002-04-01), Chiu et al.
patent: 6377217 (2002-04-01), Zhu et al.
patent: 6377440 (2002-04-01), Zhu et al.
patent: 6404614 (2002-06-01), Zhu et al.
patent: 6492883 (2002-12-01), Liang et al.
patent: 6514895 (2003-02-01), Chiu et al.
patent: 6525630 (2003-02-01), Zhu et al.
patent: 6531936 (2003-03-01), Chiu et al.
patent: 6535076 (2003-03-01), Partridge et al.
patent: 6538603 (2003-03-01), Chen et al.
patent: 6556102 (2003-04-01), Sengupta et al.
patent: 6590468 (2003-07-01), du Toit et al.
patent: 6597265 (2003-07-01), Liang et al.
patent: 6914480 (2005-07-01), Arai et al.
patent: 6977546 (2005-12-01), Stapleton
patent: 6985712 (2006-01-01), Yamakawa et al.
patent: 7305223 (2007-12-01), Liu et al.
patent: 7418251 (2008-08-01), Liu
Gordon Gray, “Enabling Cost Effective Integration Through Package Stacking”, Jan. 17-19, 2006, IWPC.
Khayo Izz
Macropoulos William
Mendolia Greg
Oakes James G.
Chiang Jack
Doan Nghia M
Finn, Esq. James S.
Paratek Microwave Inc.
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