Optimized binary adders and comparators for inputs having differ

Details Optimized binary adders and comparators for inputs having differ Optimized binary adders and comparators for inputs having differ

1996-05-13

1997-12-16

Mai, Tan V.

Boots, shoes, and leggings

364749, 3401462, G06F 750, G06F 738, G06F 702

Patent

active

056992793

ABSTRACT:
A first two-input adder computes the sum of one wider and one narrower input by combining a conventional adder for the low-order bits with an incrementer and selection logic for the high-order bits. A second three-input adder computes the sum of one wider and two narrower inputs in a similar way: the low-order bits are computed with a conventional carry save adder (CSA) followed by a carry propagate adder (CPA), while the high-order bits are computed with an incrementer and selection logic. The first and second circuits are combined to form a third arithmetic circuit that takes four input operands, the first of which is wider than the other three, and speculatively computes two results: (1) the sum of the first and second input operands; and (2) the sum of the first, third, and fourth input operands. This combined circuit contains all of the elements of the first two circuits, but shares a single incrementer. A degenerate case of the third circuit occurs when the second and third inputs are common. This degenerate case has particular application to superscalar instruction pointer updates for variable length instructions. By taking into account a priori restrictions on the possible input operands, these circuits are smaller and more efficient than conventional adders and comparators, which must be designed to deal with all possible input operands.

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