Optimized biasing scheme for NAND read and hot-carrier write ope

Details Optimized biasing scheme for NAND read and hot-carrier write ope Optimized biasing scheme for NAND read and hot-carrier write ope

1997-02-28

1998-09-29

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular connection

36518519, G11C 1606

Patent

active

058154388

ABSTRACT:
There is provided an improved method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate. A first positive pulse voltage having a ramp-rate characteristic on its leading edge is applied to the drain of the floating gate device during the read operation. Simultaneously, a second positive pulse voltage is applied to the control gate of the floating gate device during the read operation so as to overlap the first positive pulse voltage.

REFERENCES:
patent: 5589699 (1996-12-01), Araki
patent: 5591999 (1997-01-01), Momodomi et al.
patent: 5694356 (1997-12-01), Wong et al.

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