Optimize parallel testing

Details Optimize parallel testing Optimize parallel testing

2007-04-24

2007-04-24

Patel, Paresh (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

11175026

ABSTRACT:
Parallel dies testing, mostly implemented on memory ICs—Integrated Circuits, significantly reduced overall test time. In order to minimize the need for physical probing, wafer probe card technology to allow simultaneous probing, ATE—Automated Test Equipment with enough channels and CPU power to handle the parallel testing. While new devices are designed with enough channels, and probe cards are designed and manufactured for each new device, the need to purchase new ATE to benefit from the technology is a heavy burden on parallel testing. It is proposed to interpose a multiplexer between the probe card and the ATE accompanied by a system that optimizes tester resources. The proposed system will allow test houses to benefit most from their investment without paying the full penalty of keeping less capable ATE.

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