Optimization processing for integrated circuit physical design a

Details Optimization processing for integrated circuit physical design a Optimization processing for integrated circuit physical design a

1997-12-09

1999-02-09

Teska, Kevin J.

Boots, shoes, and leggings

G06F 1750

Patent

active

058703136

ABSTRACT:
One or more non-overlapping moving windows are positioned over a placement of cells for an integrated circuit chip to delineate respective subsets of cells. A fitness improvement operation such as simulated evolution is performed on the subsets simultaneously using parallel processors. The windows are either moved to specifically identified high interconnect congestion areas of the placement, or are moved across the placement in a raster type pattern such that each area of the placement is processed at least once. Exchange of misplaced cells between subsets can be accomplished by dimensioning the windows and designing the window movement pattern such that the subsets overlap. Alternatively, such exchange can be accomplished by using two sets of windows of different sizes. As yet another alternative, the improvement operation can allow misplaced cells to move to a border area outside a window. Each misplaced cell is placed on a list, and then moved to the centroid of a net of cells to which it is connected, which can be outside the subset that originally included the misplaced cell.

REFERENCES:
patent: 4630219 (1986-12-01), DiGiacomo et al.
patent: 4686629 (1987-08-01), Noto et al.
patent: 5392222 (1995-02-01), Noble
patent: 5471398 (1995-11-01), Stephens

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