Optimization of test stimulus verification

Details Optimization of test stimulus verification Optimization of test stimulus verification

1991-02-01

1994-06-21

Baker, Stephen M.

Excavating

364580, G01R 3128

Patent

active

053234014

ABSTRACT:
Optimization of test stimulus verification by analyzing test stimulus timing information against restriction rules derived from a static analysis of a digital system. The result of this analysis is used to determine test stimulus timing which cannot cause a timing violation and to remove the associated vectors from further checking. Only those vectors which can violate timing constraint rules are checked individually to find states which violate the timing rules.

REFERENCES:
patent: 4894829 (1990-01-01), Monie et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5046033 (1991-09-01), Andreason et al.
patent: 5095454 (1992-03-01), Huang
Milne, B., "Timing, Not Speed, Counts the Most When Testing Fast VLSI ICs", Electronic Design, May 29, 1986, pp. 132-142.
Kawabata, Y. et al., "PGTOOL: An Automatic Interactive Program Generation Tool for Testing New-Generation Memory Devices", 1988 International Test Conf., pp. 559-568.
Novellino, J., "Software Generates ASIC Test Programs", Electronic Design, Apr. 27, 1989, pp. 59-62.
Verhelst, B., "Using a Test-Specification Format in Automatic Test-Program Generation", IEEE Design & Test of Computers, Feb. 1990, pp. 39-45.

Affiliated with

Also associated with

Rating

Optimization of test stimulus verification does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optimization of test stimulus verification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimization of test stimulus verification will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2226212