Optimization of electronic package geometry for thermal...

Details Optimization of electronic package geometry for thermal... Optimization of electronic package geometry for thermal...

2007-08-30

2010-06-15

Geyer, Scott B (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C438S122000

Reexamination Certificate

active

07737550

ABSTRACT:
An electronic package device is disclosed including a microelectronic package and a heat sink positioned over the microelectronic package. A thermal interface element is positioned between the microelectronic package and the heat sink. The thermal interface element is elongated and has differing thicknesses along its length to enhance the dissipation of heat.

REFERENCES:
patent: 7338818 (2008-03-01), Arroyo et al.
patent: 2004/0217467 (2004-11-01), Rumer et al.
patent: 2005/0139998 (2005-06-01), Fitzgerald et al.
patent: 2006/0292840 (2006-12-01), Lin et al.
patent: 11163231 (1999-06-01), None
patent: 11317478 (1999-11-01), None
patent: 2004-4327987 (2004-11-01), None

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