Optimization of die yield in a silicon wafer “sweet...

Details Optimization of die yield in a silicon wafer “sweet... Optimization of die yield in a silicon wafer “sweet...

2005-12-27

2005-12-27

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C716S030000

Reexamination Certificate

active

06980917

ABSTRACT:
A method of increasing the wafer yield for an integrated circuit includes the steps of receiving as input a shot map, an initial orientation of a center of the shot map relative to a center of a wafer resulting in a maximum number of printable die, a usable wafer diameter, a selected yield margin, and historical yield information for each die location in the shot map; generating a plot of an estimated yield for each die location in the wafer from the historical yield information; plotting an estimated wafer yield within an area of the wafer as a function of a radius; and selecting a sweet spot radius corresponding to an area of the wafer having a wafer yield that is substantially equal to the selected yield margin for finding an offset from the initial orientation of the center of the shot map that results in a maximum wafer yield.

REFERENCES:
patent: 5305222 (1994-04-01), Nakamura
patent: 6016391 (2000-01-01), Facchini et al.
patent: 6604233 (2003-08-01), Vickery et al.

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