Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
1998-08-10
2001-06-05
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S505000, C709S241000
Reexamination Certificate
active
06243107
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to graphics processor systems and more particularly to optimizing geometry processing and the rendering of images of such processor systems.
BACKGROUND OF THE INVENTION
The tasks of traditional geometric graphics applications can be partitioned into three functional categories: structure traversal, geometry processing, and rendering. Structure traversal refers to the traversal of an application's graphics data structure, either by the application or by a graphics library.
Geometry processing refers to floating point intensive operations, such as vertex transformation and shading, that convert the image data from an applications format into a geometric format of vertices comprising the image and vertex properties, such as color. Finally, rendering refers to the process of calculating individual pixel values for the image that are stored in graphics memory based on the transformed geometric data.
Graphics processor architectures often include multiple processors or central processing units (CPUs). The individual CPUs can be similar or they can be different from each other based upon the application. However, graphics systems that have attempted to use multiple CPUs have had significant overhead due to data motion and synchronization issues. Such multiprocessor systems typically have included at least two CPUs, one or more slave threads, and at least one application thread, sometimes referred to as the master thread. In addition, each of the CPUs typically has a CPU cache. Graphics processor software typically is implemented as a sequential series of computational stages, called the graphics pipeline. Multiprocessor graphics systems could operate by assigning certain floating point pipeline stages to certain CPUs.
For example, the floating point pipeline stages might be an application stage, a geometry transform stage, a lighting stage, a texturing stage, and then several other stages before displaying on the hardware, or before the data is output to the hardware. Using this assignment system, one CPU may execute a first group of stages, and then another CPU might execute the remaining stages.
This type of assignment system fails for two reasons. The first reason is that data must be moved from one CPU to another across stage boundaries. This is a problem because hardware mechanisms for communicating between CPUs are typically very complex. They are so complex that typically both CPUs must be stalled until all the data is transferred from one CPU to the other. The second problem is that the CPUs have to be synchronized. Once again, this requires stalling the CPUs to assure that the data that is being provided is clearly synchronized from one CPU to the next. In such a system, there is the ability to rearrange the pipeline; however, the above-identified problems will still occur.
Accordingly, what is needed is a system and method in a multiprocessor graphics environment that minimizes data motion between CPUs and also minimizes overhead created by synchronization. The system should be easy to implement, should be cost effective, and should not require significant modification of existing graphics processor systems. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method and system for optimizing the performance of a graphics processor system is disclosed. The graphics processor system includes multiple CPUs. The system has at least one application thread, and in addition each CPU is assigned a slave thread. In a first aspect, the method and system comprises assigning each slave to a particular CPU and causing the master thread to move between the processors to cause each slave thread to execute its graphics pipeline. This minimizes data motion due to application inputs being transferred from CPU to CPU. The method and system further includes providing a summary of relevant changes to graphics state to each slave, thus guaranteeing correct state without requiring synchronization around state updates.
Accordingly a system and method in accordance with the present invention minimizes data motion during input and also minimizes synchronization associated therewith in a graphics processor system. In a second aspect, the method and system comprises incorporating within each slave thread the entire graphics computation pipeline. Consequently no intermediate outputs are transferred from CPU to CPU, thus minimizing output data motion.
The method and system further provides separately addressable output buffers for each slave for communication with the hardware. These output buffers are processed by the hardware in an order corresponding to the original order of inputs. Thus correct serial output is guaranteed with minimal synchronization between threads. Accordingly, a system and method in accordance with the present invention minimizes output data motion and also minimizes synchronization associated therewith in a graphics processor system. These features in both aspects enhance the performance of a graphics processor system.
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Mullis Donald Wayne
Valtin Peter Bingham
3D Labs Inc., Ltd.
Chauhan Ulka J.
Sawyer Law Group LLP
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