Optimization methods for on-chip interconnect geometries...

Details Optimization methods for on-chip interconnect geometries... Optimization methods for on-chip interconnect geometries...

2005-05-03

2005-05-03

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

C438S737000, C438S761000

Reexamination Certificate

active

06887791

ABSTRACT:
The present invention presents optimization methods for interconnect geometries that readily extend to the UDSM region for determining on-chip interconnect process parameters more realistically and accurately than in the prior art. A method for reconstruction flow that re-assembles each of a number of optimized structures into one optimized interconnect process file, such as a process technology file for extractors. This optimized process technology file can use not only extracted interconnect process parameters but also the input of LPE (Layout Parasitic Extraction) tools in physical verification stage.

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