Optimization circuitry and control for a synchronous memory devi

Details Optimization circuitry and control for a synchronous memory devi Optimization circuitry and control for a synchronous memory devi

1995-03-13

1996-08-06

Nelms, David C.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365233, 365194, G11C 1300

Patent

active

055441246

ABSTRACT:
A method and apparatus for optimizing the speed path of a memory access operation in a synchronous depending upon the present latency period for the synchronous DRAM. The improved memory device compensates the time between row address latching and column address latching (tRCD) by delaying the presentment of the column address to compensate tRCD from the time available for column address latching to valid data-out (tAA) when tRCD is the critical parameter. Optimization circuitry reduces the amount of time available for tAA and "shifts" it to the more critical parameter tRCD, enabling the optimization or reduction of the time allocated for tRCD by compensating tRCD with the extra time available for tAA. Thus, the memory access optimization circuitry enables an optimization or reduction in the total memory access time by compensating the optimized tRCD with the extra time available for tAA.

REFERENCES:
patent: 5339276 (1994-08-01), Takasugi
patent: 5402388 (1995-03-01), Wojcicki et al.

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