Optimization binarizing circuit

Details Optimization binarizing circuit Optimization binarizing circuit

1994-09-28

1999-06-08

Lee, Thomas D.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358448, 358455, 358466, 382270, 382274, H04N 140

Patent

active

059108509

ABSTRACT:
Disclosed herein is a binarizing circuit comprising a setting circuit for responding to changes in density of inputted image data based on a unique algorithm and for setting an optimal binarizing density level, a delay circuit for delaying the inputted image data for a predetermined time period and for outputting delayed image data, and a comparator for comparing the delayed image data supplied from the delay circuit with the binarizing density level set by the setting circuit and for generating optimal binarized image data in accordance with the changes in density of the inputted image data. When an image of a low contrast is read from an original, character portions of a low contrast can be reproduced, with background noise being eliminated to achieve excellent binarizing.

REFERENCES:
patent: 5138671 (1992-08-01), Yokoyama
patent: 5307425 (1994-04-01), Otsuka

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