Optimization apparatus that decreases delays in pipeline...

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C717S150000, C717S151000, C717S160000

Reexamination Certificate

active

06993756

ABSTRACT:
An optimization apparatus is capable of improving the execution efficiency of a loop that includes a loop carry dependency between consecutive iterations of the loop. For example, a value resulting from one iteration is used in an immediately following iteration. When the arithmetic expression “a[i+1]=a[i]*3+2;” is included in a loop body, and a value resulting from the arithmetic expression “a[i+1]=a[i]*3+2;” in one iteration is used in a following iteration, execution delays occur in pipeline processing of the loop. Here, the arithmetic expression “a[i+1]=a[i]*3+2;” is transformed into the arithmetic expression “a[i+4]=a[i]*81+80;” to expand the dependency distance. By doing so, the execution delays can be decreased.

REFERENCES:
patent: 5179702 (1993-01-01), Spix et al.
patent: 5265253 (1993-11-01), Yamada
patent: 5303357 (1994-04-01), Inoue et al.
patent: 5386562 (1995-01-01), Jain et al.
patent: 5481723 (1996-01-01), Harris et al.
patent: 5842022 (1998-11-01), Nakahira et al.
patent: 6247173 (2001-06-01), Subrahmanyam
patent: 6-103083 (1994-04-01), None
Digital Equipment Corporation, “KAP for DEC Fortran for Digital UNIX”, section 4.5.21, Dec. 1996.
Larus, J.R., “Loop-level parallelism in numeric and symbolic programs”, Parallel and Distributed Systems, IEEE Transactions on vol.: 4, Issue: 7, Jul. 1993, pp.: 812-826.
Giovanni Agosta, “High-Level Dataflow and Loop Optimization for High-Performance Parallel Computing through the SUIF Compiler”, Nov. 27, 2000, retrieve from internet <http://www.elet.polimi.it/upload/agosta/ACA/optimization.pdf> on Sep. 11, 2004.
“Improving the Ratio of Memory Operations to Floating-Point Operations in Loops”, by Steve Carr and Ken Kennedy, ACM Transactions on Programming Languages and Systems, vol. 16, No. 6 Nov. 1994, pp. 1768-1810.
Kainaga, M. et al., “A Fast Execution of Recurrrences on Superscalar Processors”, Transactions of Information Processing Society of Japan, vol. 34, No. 12, pp. 2592-2598.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Optimization apparatus that decreases delays in pipeline... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optimization apparatus that decreases delays in pipeline..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimization apparatus that decreases delays in pipeline... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3558657

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.