Optimal simplification of constraint-based testbenches

Details Optimal simplification of constraint-based testbenches Optimal simplification of constraint-based testbenches

2011-03-22

2011-03-22

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S101000, C716S104000, C716S119000

Reexamination Certificate

active

07913208

ABSTRACT:
Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected, and a merged model is built that eliminates the candidate redundant gate. If the candidate redundant gate is within the merged constraint cone the pre-merge model is used to validate redundancy of the candidate redundant gate. However, if the candidate redundant gate is not within the merged constraint cone the merged model is instead used to validate redundancy of the candidate redundant gate.

REFERENCES:
patent: 4960724 (1990-10-01), Watanabe et al.
patent: 6298319 (2001-10-01), Heile et al.
patent: 6301687 (2001-10-01), Jain et al.
patent: 6311317 (2001-10-01), Khoche et al.
patent: 6678644 (2004-01-01), Segal
patent: 6714902 (2004-03-01), Chao et al.
patent: 6964027 (2005-11-01), Kucukcakar et al.
patent: 7260799 (2007-08-01), Baumgartner et al.
patent: 2004/0153323 (2004-08-01), Charney et al.
patent: 2007/0136701 (2007-06-01), Baumgartner et al.
“Using Constraint Techniques for a Safe and Fast Implementation of Optimality-Based Reduction,” by Yahia Lebbah et al., Symposium on Applied Computing, Mar. 11-15, 2007, Seoul, Korea.
“Testing Strategies for Simulation Optimization,” by Russell R. Barton, Proceedings of 1987 Winter Simulation Conf.
“Verification Flow Optimization using an Automatic Coverage Driven Testing Policy,” Younes Lahbib et al., IEEE Paper 0-7803-9727-4/06 (2006).
“Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives,” IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, by Srimat T. Chakradhar et al., vol. 16, No. 11, Nov. 1997.
“Circuit Partitioning with Logic Perturbation,” by David Ihsin Cheng et al.; Report for NSF Grant MIP 9419119; Universithy of Electrical and Computer Engineering, UC Santa Barbara; available in ICCAD '95 Proceedings of the 1995 IEE/ACM Int'l Conf. on CAD, ISBN: 0-8186-7213-7; 1995.

Affiliated with

Also associated with

Rating

Optimal simplification of constraint-based testbenches does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optimal simplification of constraint-based testbenches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimal simplification of constraint-based testbenches will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2773737