Optimal retiming of synchronous logic circuits

Details Optimal retiming of synchronous logic circuits Optimal retiming of synchronous logic circuits

1994-12-27

1996-09-10

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, 364491, G06F 1750

Patent

active

055551882

ABSTRACT:
A process for optimally retiming until delay sequential circuits involves first computing the optimal clock period of the circuit by a novel computation method and then relocating the flip flops in the circuit to provide the computed optimal clock period for the circuit. The optimal clock period is computed by viewing the circuit as an interconnection of path segments with pre-specified delays, constructing a path graph of the circuit that has as many vertices as there are latches in the circuit, and formulating an integer linear program to compute the minimum clock period .phi..sub.opt for which the path graph has no critical cycles. .phi..sub.opt is also the optimal clock period of the circuit.

REFERENCES:
patent: 3617714 (1971-11-01), Kernighan et al.
patent: 4263651 (1981-04-01), Donath et al.
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5003487 (1991-03-01), Drumm et al.
patent: 5005136 (1991-04-01), Van Berkel et al.
patent: 5210700 (1993-05-01), Tom
patent: 5262959 (1993-11-01), Chkoreff
patent: 5282147 (1994-01-01), Goetz et al.
patent: 5287289 (1994-02-01), Kageyama et al.
Paulin et al., "HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis," 23rd Design Automation Conference, pp. 587-594.
Keutzer, "DAGON: Technology Binding and Local Optimization by DAG Matching," 24th ACM/IEEE Design Automation Conference, 1987, pp. 341-347.
Pangrle et al., "Design Tools For Intelligent Silicon Compilation," IEEE Transactions On Computer-Aided Design, vol. CAD-6, No. 6, Nov. 1987, pp. 1098-1112.
Marek-Sadowska et al., "Timing Driven Placement," 1989 IEEE, pp. 94-97.
Mahmood et al., "A Formal Language Model of Local Microcode Synthesis," Formal VLSI Specification and Synthesis:VLSI Design Methods-l, 1990, pp. 23-41.

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