Boots – shoes – and leggings
Patent
1994-09-13
1997-06-10
Teska, Kevin J.
Boots, shoes, and leggings
364490, G06F 1700
Patent
active
056382936
ABSTRACT:
A cell placement is generated for a microelectronic circuit chip. Interconnect points for cell nets are calculated, for example, as gravity points of the cells of the respective nets. Optimal positions for external connection terminals or pads along the border of the circuit are calculated as being the closest positions to the respective interconnect points. The total wirelength of the placement is calculated as including the distances between the interconnect points and the respective pads. Where initial location of the pads results in overlap thereof, clusters of pads are identified and expanded to remove the overlap. Concatenated overlapping clusters resulting from expansion are treated as new clusters and subsequently expanded until all overlap is eliminated. The centers of gravity of the clusters are preserved. During the overlap removal process, initial rectangular coordinates of the pad positions are converted into linear coordinates along the border. After the overlap is eliminated, the linear coordinates are converted back to rectangular coordinates.
REFERENCES:
patent: 3603771 (1971-09-01), Isett
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 5072402 (1991-12-01), Ashtaputre et al.
patent: 5119313 (1992-06-01), Shaw et al.
patent: 5231590 (1993-07-01), Kumar et al.
patent: 5267176 (1993-11-01), Antreich et al.
patent: 5267177 (1993-11-01), Sato et al.
patent: 5303161 (1994-04-01), Burns et al.
patent: 5404313 (1995-04-01), Shiohara et al.
Wang, Deborah C., Pad Placement and Ring Routing for Custom Chip Layout, IEEE, 1990, Paper 10.3, pp. 193-199.
Yao, Xianjin and Liu, L.C.,A New Approach to the Pin Assignment Problem, IEEE Transactionson Computer-Aided Design, vol. 8, No. 9, Sep., 1989, pp. 999-1006.
Pedram, Massoud, Marck-Sadowska, Malgorzara, Kuh, Ernest S., Floorplanning with Pin Assignment, IEEE, 1990, pp. 98-101.
Cong, Jingsheng (Jason), Pin Assignment with Global Routing, IEEE, 1989, pp. 302-305.
Yao et al., "A New Approach to the Pin Assignment Problem", ACM/IEEE Design Automation Conf., 1988, pp. 566-572.
Pedram et al., "I/O Pod Assignment based on the Circuit Structure", Proc of 1991 IEEE Int'l Conf on Comp Design - VLSI Comp. pp. 314-318.
Cong, "Pin Assignment w/Global Routing for General Cell Designs", IEEE Trans on CAD, vol. 10, No. 11, Nov. 1991, pp. 1401-1412.
Wang, et al., "Simultaneous Pin Assignment & Global Wiring For Custom VLSI Design", Proc of 1991 IEEE Conf on Comp Design, pp. 2128-2131.
D'Haeseleer Patrik
Scepanovic Ranko
LSI Logic Corporation
Teska Kevin J.
Walker Tyrone V.
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