Optimal location of a digital sync pattern

Details Optimal location of a digital sync pattern Optimal location of a digital sync pattern

2000-05-12

2004-11-30

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

Reexamination Certificate

active

06826245

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to determining an optimal location for each of a sequence of digital signal sync patterns.
BACKGROUND OF THE INVENTION
A digital data stream from an optical storage or other storage device or in general communications, contains a unique binary pattern, called a “sync pattern,” that appears at predetermined time intervals within the digital bit stream. An ability to detect the sync pattern within the serial bit stream is required in order to recover the original data encoded in the communication. One problem encountered here is the presence of dirt or other foreign material (fingerprints, organic or inorganic substances, etc.) and scratches on the medium or defects that are stamped or otherwise embedded in the media during manufacturing, which can alter the data that are read. Another problem is signal degradation, due to noise or other interference with signal transmission and/or processing. Presence of such interfering alterations can damage the sync pattern and/or can cause the sync pattern to appear earlier or later than expected in the bit stream. If the sync pattern cannot be detected, data synchronization may be temporarily lost, resulting in elevated data error rates before the data are demodulated and corrected.
In a typical implementation, a sync window is used to search for the sync pattern. Once a valid sync pattern is found, normally requiring a perfect match with a reference pattern, the sync detect logic will not begin looking for the next sync pattern until the start of the next sync window, which is assumed to be located at an “ideal distance” B bits beyond the immediately preceding sync pattern. This approach prevents the sync detect logic from triggering on a false sync pattern that may appear within the data stream due to the presence of corrupted data within the bit stream. A sync window is typically 2N+1 bits wide, where N is a positive integer, spaced apart at an ideal or reference distance from the last sync pattern found. If the true sync pattern appears N or fewer bits too soon or N or fewer bits too late, relative to the identified and immediately preceding sync pattern, the sync pattern can still be detected, and a segment of original data following the present sync pattern can be demodulated correctly.
If data from the storage media are very corrupted, or if the transmission channel is not well designed, the sync pattern may be shifted more than a selected number of bits away from the ideal distance B, the sync pattern will fall outside the sync window, and the present sync pattern will be missed. If the sync window width H, typically 2N+1 bits, is increased to decrease the probability of not recognizing and capturing the present sync pattern (a type 1 error), the probability of sensing a false sync pattern (a type 2 error) is increased. It is also possible that a (modified) sync pattern appears within the window, but this sync pattern has one or more bit errors that prevent the sync comparison logic from detecting the presence of this sync pattern.
A typical sync pattern system used today assumes that the first sync pattern found within the sync window is the correct (and only) sync pattern and does not continue the search for any other sync patterns within the present sync window. This strategy may be counter-productive as the window width, H bits, is increased, and the probability of a type 2 error increases.
What is needed is a system that allows an arbitrarily wide sync window to be used and that identifies the “best” location for the next sync pattern, based on one or more metrics or other criteria for a “best fit.” Preferably, this system should decrease the probability of occurrence of a type 1 error and/or of a type 2 error. Preferably, the system should be flexible enough to allow arbitrary changes to be implemented for the sync window parameters (H, B, S, etc.) and to allow changes in the parameters used for the best fit criterion or criteria.
SUMMARY OF THE INVENTION
These needs are met by the invention, which provides a system that examines each of H candidates (H=2N+1 or another positive integer) for a reference location of a signal stream sync pattern, identifies one or more candidate locations that provide a best fit, and compares the metric for a best fit location with a threshold metric value. The reference location for a sync pattern window may be the beginning, center or end of the window or any other suitable location within or measured relative to the window. The metric may be based on the number of bit pattern mismatches or on the number of bit pattern matches. If the metric value for a candidate best fit location is not at least as favorable as the threshold metric value, the candidate best fit location does not qualify, and the system uses another approach to estimate a best fit for a reference location for the next sync pattern. The sync window width, H bits, the ideal distance, B bits, and/or the width of the sync pattern, S bits, may be selected and fixed, or one or more of these parameters may be varied dynamically in response to certain error rates sensed by the system. The digital signal stream may be a general communication or may arise from a special purpose, such as data from a storage medium.
A Sync Control machine begins in an Idle State. When read channel data enters the system, Sync Control enters a Sync Sequence Validation state, which verifies that the two sync patterns have the expected spacing. For a bit stream with a DVD media source, the Sync Sequence Validation state is also used to determine if the two sync patterns are in an expected numerical order. When sync validation is completed, Sync Control moves to the next process. When DVD media signals are present, the next process is an ECC Block Validation process, which determines the beginning of an ECC block; this process is skipped for CD media signals (which includes CDROM, CDRead, CDRead/Write and CDAudio herein). In the next Sync Control process, Data Acquisition, a sync detect engine attempts to identify consecutive sync patterns and to transfer this information, together with the actual bit stream, to a demodulator.


REFERENCES:
patent: 5757869 (1998-05-01), Sands et al.
patent: 6154468 (2000-11-01), Lin et al.
patent: 6414920 (2002-07-01), Lee
patent: 6536011 (2003-03-01), Jang et al.

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