Optimal integrated circuit generation

Details Optimal integrated circuit generation Optimal integrated circuit generation

1990-04-18

1993-08-17

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364488, 36471501, G06F 1560, G06F 748

Patent

active

052375137

ABSTRACT:
An integrated circuit structure is generated to perform a given combinational logic function. A data processing system generates the integrated circuit structure when provided with an input specification of the function to be performed by the structure. The resulting integrated circuit structure is comprised of both restoring logic networks and pass logic networks. The structure is generated by initially representing the function in a number of multidimensional boolean spaces. Subsequently, these spaces are manipulated to generate the resulting pass and restoring logic networks.

REFERENCES:
patent: 4541067 (1985-09-01), Whitaker
patent: 4566064 (1986-01-01), Whitaker
patent: 4591993 (1986-05-01), Griffin et al.
patent: 4622648 (1986-11-01), Whitaker
patent: 4697241 (1987-09-01), Lani
patent: 4709226 (1987-11-01), Christopher
patent: 4792909 (1988-12-01), Serlet
patent: 4916627 (1990-04-01), Hathaway
M. Y. Tsai, "Pass Transistor Networks in MOS Technology: Synthesis, Performance, and Testing," Proc. of IEEE Conf., 1983, pp. 509-512.
O. Ishizuka, "Synthesis of a Pass Transistor Network Applied to Multi-Valued Logic," Proc. of the 16th EEEE ISMVL, 1986, pp. 51-57.
O. Ishizuka and J. Xu, "Simplification of Pass Transistor Networks and its Applications," Proc. of 17th IEEE ISMVL, 1987, pp. 292-297.
R. K. Brayton and C. McMullen, "The Decomposition and Factorization of Boolean Expression," IEEE Symposium on Circuits and Systems, 1982, pp. 49-54.
E. Detjens et al., "Technology Mapping in MIT," Proc. of IEEE Int'l Conf. on CAD, 1987, pp. 116-119.
Brayton et al., "MIS: A Multiple-Level Optimization System," Proc. of Int'l Workshop on Logic Synthesis, 1987.
W. D. Becher, "Karnaugh Map Minimization," Logical Design Using Integrated Circuits, 1977, Hayden Book Co. USA, pp. 93-119.
S. Whitaker, "Pass-Transistor Networks Optimize n-MOS Logic," Electronics, pp. 144-148.
R. Brayton et al., "Multiple-Level Logic Optimization System," IEEE Inter Conf. on CAD, 1986, pp. 356-359.

Affiliated with

Also associated with

Rating

Optimal integrated circuit generation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optimal integrated circuit generation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimal integrated circuit generation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2249546