Optimal error correction method for zero byte time slot intercha

Details Optimal error correction method for zero byte time slot intercha Optimal error correction method for zero byte time slot intercha

1987-06-30

1988-12-27

Smith, Jerry

Excavating

H03M 1300, H04L 100

Patent

active

047946040

ABSTRACT:
A method and circuit for exploiting the characteristics of the ZBTSI algorithm by using the relationship of the data octet and the octets adjacent thereto to detect error conditions such as violations of the DS1 ones density criteria for detection of transmission channel errors in the ZBTSI decoder. This relationship provides an optimized partial error correction technique which minimizes error multiplication in the PCM transmission channels.

REFERENCES:
patent: 4747098 (1988-05-01), Huang et al.
patent: 4747112 (1988-05-01), Blondeau, Jr. et al.
IBM Tech. Disclosure Bull., Glick et al., "Single-Error Correction, Double-Error Detection Code. . .", vol. 15, No. 1, Jun. 1972, pp. 130-134.

Affiliated with

Also associated with

Rating

Optimal error correction method for zero byte time slot intercha does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optimal error correction method for zero byte time slot intercha, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimal error correction method for zero byte time slot intercha will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-873202