Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1975-12-31
1977-04-05
Heyman, John S.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307205, 307270, 307DIG1, 330 35, H03K 3353, H03K 5159, H03K 1908
Patent
active
040164314
ABSTRACT:
An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=1nM, ##EQU1## AND WHERE THE CAPACITANCE OF ANY INTERMEDIATE STAGE IS C.sub.P =.sqroot.C.sub.(P.sub.-1) .sup.. C.sub.(P.sub.+1). Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one. The utility of these design parameters in instances where the ratio of capacitance is greater than a thousand to one, and the number of intermediate stages is ten or greater is particularly apparent.
REFERENCES:
patent: 3378783 (1968-04-01), Gibson
Lin et al., "An Optimized Output Stage for MOS Integrated Circuits"; IEEE Journal of Solid-State Circuits; vol. SC-10, No. 2, pp. 106-109; Apr. 1975.
Henle Robert Athanasius
Ho Irving Tze
Anagnos Larry N.
Heyman John S.
International Business Machines - Corporation
Thomson James M.
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