Optimal design method and apparatus for synchronous digital circ

Details Optimal design method and apparatus for synchronous digital circ Optimal design method and apparatus for synchronous digital circ

1993-11-02

1999-04-27

Chin, Wellington

Pulse or digital communications

Synchronizers

371 1, 375359, H04L 700

Patent

active

058987428

ABSTRACT:
Optimal design method and apparatus for synchronous digital circuits by retiming through selective flipflop positioning and electronic circuit configuration produced by executing the method. The method is for designing a synchronous digital electronic circuit that comprises cells and clocked flipflops interconnected by nets and running at a predetermined clock period, operates as follows. First, uniform-directedly as starting from any cell for any sub-path emanating therefrom its associated delay is accumulated. Next, if for such sub-path the accumulation result exceeds a predetermined integer number of clock periods. The sub-path in question is signalled for subsequent provision with such integer number of flipflops and its accumulation is terminated. Finally, all elementary cell-to-cell connections are provided with flipflops in minimal accordance with said signalling. The invention is particularly advantageous with large circuits such as used in digital video processors and with small clock periods.

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"Don't Get Skewed on Your Next ASIC Design" E. Ryherd, EDN Electrical Design News, vol. 36, No. 18 pp. 139-144.
"Retiming Synchronous Circuitry" CH.E. Leiserson et al, Algorithmica '91, pp. 5-35.

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